Infineon Technologies Ag

Infineon Technologies Austria Ag

Martin Pölzl

Franz Hirler

Ralf Siemieniec

Walter Rieger

Martin Henning Vielemeyer

Ralf Henninger

Gerhard Nöbauer

Oliver Häberlen

Joachim Krumrey

Manfred Kotek

Hans Weber

Michael Treu

Robert Paul Haase

Heimo Hofer

A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.

Method of manufacturing a semiconductor die

A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.

Power transistor with at least partially integrated driver stage

A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.

Electronic circuit having adjustable transistor device

In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement () is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array () with cell array trenches () each containing a field electrode structure () and a gate electrode structure (). The field electrode structure () is electrically conductively connected to the source metallization () by a connection trench () in the cell array ().

Power transistor arrangement and method for fabricating it

When fabricating trench power transistor arrangements () with active cell array trenches () and passive connecting trenches (), the cell array trenches () are provided in greater width than the connecting trenches (). An auxiliary layer () is deposited conformally onto a lower field electrode structure () in the cell array trenches () and the connecting trenches () and is etched back as far as the top edge in the connecting trenches (), which removes it from the cell array trenches (). The auxiliary layer () allows the gate oxide () to be patterned without a complex mask process. An edge trench (), with an electrode, on the potential of the field electrode structure () shields the cell array () from a drain potential.

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.

Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

Field-effect-controllable semiconductor component and method for fabricating the component

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Growing community of inventors

Ossiach, Austria

Martin Pölzl