Infineon Technologies Ag

Qimonda Ag

Martin Popp

Lars Heineck

Till Schloesser

Dietmar Temmler

Stephan Kudelka

Harald Seidl

Hans-Peter Moll

Jörn Lützen

Rolf Weis

Bernd Goebel

Till Schlösser

Werner Graf

Kristin Schupke

Andreas Wich-Glasen

Peter Baars

Helmut Horst Tews

Bernhard Sell

Martin Gutsche

Wolfgang Roesner

Frank Jakubowski

Gerhard Enders

Dirk Manger

Richard Johannes Luyken

Juergen Faul

Klaus Muemmler

Ulrike Gruening-von Schwerin

Alexander Michaelis

Uwe Schroeder

Stefan Jakschik

J&uuml;rgen Lindolf

Juergen Holz

Dirk Schumann

Peter Lahnor

Alfred Kersch

Marc Strasser

Frank Richter

Bernd Hintze

Thomas Schuster

Annette Sänger

Jens Hahn

Arnd Scholz

Uwe Schilling

Daniel Koehler

Michael Sesterhenn

Werner Steinhögl

Andrei Josiek

Johann Steinmetz

Kerstin Pomplun

Gouri Sankar Kar

An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

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One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

Word line to bit line spacing method and apparatus

An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

Memory cell array comprising wiggled bit lines

One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

Transistor, memory cell, memory cell array and method of forming a memory cell array

An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25&#x2266;DL/DC&#x2266;1/1.75.

Integrated circuit having a memory cell array and method of forming an integrated circuit

In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Method for producing a trench transistor and trench transistor

A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Memory cell array and method of forming the same

Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell

Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric to produce the gate stacks. An oblique implantation of an oxidation-inhibiting implantation species is carried out into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks. Oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks and a second oxide layer on uncovered side faces of the second layer of the gate stacks is carried out, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

Process for producing a plurality of gate stacks which are approximately the same height and equidistant on a semiconductor substrate

The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow Ican be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

Field effect transistor and method for fabricating it

A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes are arranged in a high packing density in a first section and are assigned to selection transistors of memory cells, and are arranged in a low packing density in a second section and are assigned to transistors of logic circuits. After a processing of the selection transistors, the encapsulated gate electrodes are uncovered in the second section and are subsequently doped in the same way in each case simultaneously with the respectively assigned source/drain regions. Together with a subsequent siliciding of the gate electrodes and of the source/drain regions, the performance of the transistors in the second section is significantly increased with little additional outlay.

Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate

A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

Memory cell having a thin insulation collar and memory module

In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it

In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

Integrated semiconductor memory with wordlines conductively connected to one another in pairs

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Dresden, Germany

Martin Popp