Advanced Micro Devices Corporation

Sigmatel, Inc.

Martin Paul Piorkowski

John J Wuu

Russell J Schreiber

Keith Allen Kasprak

Peter Normand Labrecque

Srinivas R Sathu

Atif Habib

A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Memory with expandable row width

A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.

Timer for use dual voltage supplies

Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element.

Memory elements having configurable access duty cycles and related operating methods

A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.

Voltage shifting word-line driver and method therefor

A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address. A sense amplifier generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns in response to a sense amp enable signal. A sense amp enable signal generator generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals.

Growing community of inventors

Austin, TX, United States of America

Martin Paul Piorkowski