Intel Corporation

Martin Ostermayr

Georg Seidemann

Harald Gossner

Thomas Wagner

El Mehdi Boujamaa

Yang Hong

Walther Lutz

Joachim Assenmacher

Klaus Herold

Bernd Waidhas

Peter Baumgartner

Wolfgang Molzer

Richard Geiger

Georgios Panagopoulos

Michael Langenbuch

Johannes Rauh

Joachim Singer

IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

Buried power rails integrated with decoupling capacitance

A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

Semiconductor dies and devices with frontside and backside coils for inductive coupling

A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Semiconductor structure and method for forming a semiconductor structure

A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.

Semiconductor dies and devices with a coil for inductive coupling

A memory circuit, comprises a first set of memory cells configured to operate in a direct access mode or in a refresh mode and a second set of memory cells configured to operate in the direct access mode and in the refresh mode. The memory circuit further comprises a controller configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Memory circuit and method for operating a first MRAM and a second MRAM set of memory cells configured to operate in a direct access mode and/or refresh mode

A memory circuit (), comprises a first set of memory cells () configured to operate in a direct access mode or in a refresh mode and a second set of memory cells () configured to operate in the direct access mode and in the refresh mode. The memory circuit () further comprises a controller () configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Memory circuit and method for operating a first and a second set of memory cells in direct memory access mode with refresh

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Oberhaching, Germany

Martin Ostermayr