International Business Machines Corporation

Globalfoundries Inc.

Intel Corporation

Martin Ohmacht

Alan G Gara

Dong Chen

Philip Heidelberger

Mark Edwin Giampapa

Matthias Augustin Blumrich

Valentina Salapura

Krishnan Sugavanam

Dirk Hoenicke

Pavlos Michael Vranas

Paul William Coteus

Burkhard Steinmacher-Burow

Todd Edward Takken

Kai-Ting Amy Wang

Rudolf Adriaan Haring

Alexandre E Eichenberger

Thomas M Gooding

Gerard Vincent Kopcsay

Peter Boyle

Ralph E Bellofatto

Norman Christ

Maged M Michael

Ravi Nair

Marcel Mitran

Bruce Martin Fleischer

Thomas Winters Fox

Raul Esteban Silvera

Sameer Kumar

Robert Matthew Senger

Matthew Roger Ellavsky

Luis H Ceze

Robert Mawhinney

Michael K Gschwind

Robert William Wisniewski

Kathryn Mary O'Brien

Mark Gregory Megerian

Shawn Anthony Hall

James Anthony Marcella

George L Chiu

Noel A Eisley

Burkhard D Steinmacher-Burow

David L Satterfield

Yutaka Sugawara

Jose R Brunheroto

Don Darrell Reed

Changhoan Kim

Constantinos Evangelinos

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Vijayalakshmi Srinivasan

Hans Mikael Jacobson

John A Gunnels

Thomas Mario Cipolla

Sameh W Asaad

John Kevin O'Brien

Mark James Jeanson

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Dong Chen Chen

Charles David Wait

Mark Graham Stoodley

Todd Alan Inglett

Jon K Kriegel

Jeffrey John Parker

Craig Brian Stunkel

Douglas R Miller

Amith R Mamidala

Xiaotong Zhuang

Kristan D Davis

Michael B Mundy

Richard A Swetz

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Thomas A Liebsch

Brant L Knudson

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

Charles Ray Johns

James Allan Kahle

Steven Michael Douskey

Yaoqing Gao

Xin Zhang

Paul Gregory Crumley

James C Sexton

Dietmar Schmunkamp

Abdullah Kayi

Alessandro Morari

Lance G Hehenberger

Brandon Edward Schenck

Hans Boettiger

Daniel J Littrell

Phillip Heidelberger

Moyra Kathleen McManus

A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.

Transactional lock elision with delayed lock checking

An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.

Global virtual address space consistency model

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Combined group ECC protection and subgroup parity protection

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Store operations to maintain cache coherence

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Avoiding data conflicts includes initiating a transactional lock elision transaction containing a critical section, executing the transactional lock elision transaction including the critical section, and checking a status of a lock prior to a commit point in the transactional lock elision transaction executing, wherein the checking the status occurs after processing the critical section. A determination of whether the status of the lock checked is free is made and responsive to a determination the lock checked is free, a result of the transactional lock elision transaction is committed.

In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.

Cache as point of coherence in multiprocessor system

A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Multiprocessor system with multiple concurrent modes of execution

Avoiding data conflicts includes initiating a transactional lock elision transaction containing a critical section, executing the transactional lock elision transaction including the critical section, and checking a status of a lock prior to a commit point in the transactional lock elision transaction executing, wherein the checking the status occurs after processing the critical section. A determination of whether the status of the lock checked is free is made and, responsive to a determination the lock checked is free, a result of the transactional lock elision transaction is committed.

Code versioning for enabling transactional memory region promotion may include receiving a portion of candidate source code; outlining the portion of candidate source code received for parallel execution; wrapping a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at run time; and generating an outlined code portion comprising multiple loop versions using a processor.

Code versioning for enabling transactional memory promotion

Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Local bypass for in memory computing

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Yorktown Heights, NY, United States of America

Martin Ohmacht