Onespin Solutions Gmbh

Martin Müller-Brahms

Stefan Höreth

Thomas Rudlof

The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behavior of the modified representation of the logic circuit differs from functional behavior of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behavior of the modified representation of the logic circuit from the functional behavior of the initial representation of the logic circuit.

System and method for verification and generation of timing exceptions

For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of several pre-defined different implementation alternatives is determined in each case and inserted into the reference description in place of the respective multiplication function, in order subsequently to execute the equivalence test with the reference description changed thereby. In this way, the structural equivalence between the reference description and the digital circuit to be verified can be substantially increased, which speeds up the verification process overall.

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Munich, Germany

Martin Müller-Brahms