Nxp USA, Inc.

Martin Mienkina

Joseph Charles Circello

Carl Culshaw

Quyen Pho

Osvaldo Israel Romero Cortez

Guillaume Perret

Avni Arora

A requestor of a data processing system provides read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size onto a system interconnect. A memory array stores write data and corresponding error correction code (ECC) check bits in response to write access requests and provides read data and corresponding ECC check bits for the read data in response to read access requests. A memory controller executes a read-modify-write (RMW) sequence between a store buffer and the memory array to implement a partial write transaction in response to a partial write access request, in which the memory controller stores the partial write data into the store buffer upon receiving the partial write access request and suppresses signaling of ECC errors to the requestor during the RMW sequence.

Memory controller which implements partial writes with error signaling

A System on Chip (SoC) includes a first core coupled to an interconnect; a second core coupled to the interconnect; a memory coupled to the interconnect and including a plurality of evenly sized partitions; and storage circuitry configured to store memory configuration information. The memory configuration information defines a memory configuration and is configured to indicate a series of swappable segments for each core of the SoC by indicating, for each core, a first number of partitions of the memory assigned to each of a first swappable segment and a second swappable segment for the core, the first swappable segment designated as an active segment and the second swappable segment designated as a first backup segment, and an enable indicator to indicate whether or not to assign the first number of partitions to a third swappable segment designated as a second backup segment.

Memory configuration within a data processing system

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Bystrice Nad Olsi, Czechia

Martin Mienkina