Nxp USA, Inc.

Freescale Semiconductor,inc.

Other

Martin Mienkina

Mohit Arora

Prashant Bhargava

Wangsheng Mei

Lukas Vaculik

Radomir Kozub

Ludek Slosarcik

Joseph Charles Circello

James Robert Feddeler

Carl Culshaw

Leos Chalupa

Yan Xiao

Pavel Grasblum

Larry Alan Woodrum

Sudhi R Proch

David Eromosele

Michael Galda

Martin Sebest

Peter Moravcik

A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

System and method of limiting access of processors to hardware resources

An electric power meter for measuring electric power is provided. The power meter has a frequency domain converter arranged to convert a sequence of digital voltage samples from the time domain to a frequency domain obtaining digital voltage frequency components, and to convert a sequence of digital current samples from the time domain to the frequency domain obtaining digital current frequency components. The electric power meter also has a frequency domain correction unit arranged to correct the voltage frequency components and the current frequency components by multiplying at least one frequency component of the current frequency components and the voltage frequency components with a complex correction factor using a complex multiplication unit. Electric power is computed by an energy calculation unit.

Electric power meter

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.

Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

There is provided an energy consumption meter device comprising including a processor arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using &#x394;E using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n&#x2212;1]. The processor will then calculate a relative delay Td' using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td&#x2032; with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.

Low jitter pulse output for power meter

This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.

Clock circuit and method for providing an electronic device with an adjustable clock signal

A digital signal processor (DSP) includes a CPU, and a DMA controller. The DMA controller transfers data from a source to a destination as a function of an initialization command from the CPU. The DMA controller has a logic unit that performs filter operations and other arithmetic operations on-the-fly on a data stream transferred therethrough. The filter operations include multiplication by filter coefficients and addition, without processing by the CPU. The DMA controller may have subsets of hardware configurations that can perform different operations that are selectable as a function of the initialization command.

DMA controller with arithmetic unit

The embodiments described herein provide devices and methods to facilitate ripple control communication. Specifically, the embodiments provide devices and methods for decoding ripple control data from ripple signals, such as ripple signals that have been superimposed over power signals used to transmit power. These embodiments provide devices and methods that use band-pass filter, signal multiplier, fast and slow low-pass filters, and accumulate a difference between outputs of these slow and fast low-pass filters. This accumulated difference is then used to decode the ripple control data.

Systems and methods for ripple communication decoding

A method and apparatus for performing touch detection within a touch sensing application is described. Touch sensor signal data is received, a first filtering of the received touch sensor signal data to create a first filtered data signal is performed, a second filtering of the received touch sensor signal data to create a second filtered data signal is also performed, a difference between the first and second filtered data signals to determine a delta value is calculated, and an occurrence of a touch based at least partly on the determined delta value is determined.

Method for performing touch detection and touch detection module therefor

A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

Method for low power boot for microcontroller

A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.

Sin-Cos sensor arrangement, integrated circuit and method therefor

A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

System for compensating for variations in clock signal frequency

A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.

Growing community of inventors

Bystrice, Czechia

Martin Mienkina