Dell Products Inc.

Martin McAfee

Bharath Vasudevan

Louis N Castro

Kevin Lee Miller

Robert L Nance

Robert S Tung

An information handling system includes first and second input/output (I/O) controllers, a detector for detecting an I/O controller failure, and an I/O recovery unit. The first I/O controller adaptively controls a first and a second I/O slot. The second I/O controller adaptively controls a third and a fourth I/O slot. Lastly, the I/O recovery unit, responsive to a detected I/O controller failure, operatively couples/decouples the first and second I/O slot to/from the first I/O controller, operatively couples/decouples the third and fourth I/O slot to/from the second I/O controller, and operatively decouples/couples the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure.

Recovering from a failed I/O controller in an information handling system

An information handling system includes first and second I/O controllers, a detector for detecting an I/O controller failure, and an I/O recovery unit. The first I/O controller adaptively controls a first and a second I/O slot. The second I/O controller adaptively controls a third and a fourth I/O slot. Lastly, the I/O recovery unit, responsive to a detected I/O controller failure, operatively couples/decouples the first and second I/O slot to/from the first I/O controller, operatively couples/decouples the third and fourth I/O slot to/from the second I/O controller, and operatively decouples/couples the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure.

Method and apparatus for recovering from a failed I/O controller in an information handling system

A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Dynamic reconfiguration of PCI express links

A method of responding to a thermal trip signal generated by a processor of a system having multiple processor nodes. If a processor overheats beyond a critical temperature, a temperature monitor receives the thermal trip signal, and turns off an enable signal to a voltage control module that control power to the processors. The temperature monitor also triggers a system reset. Upon reset, the temperature monitor ensures that all nodes, other than the node with the overheated processor, return to an operational state.

Multi-processor system recovery using THERMTRIP signal

Dynamic reconfiguration of PCI Express links

A debugging circuit capable of debugging a plurality of possible microprocessors, and a switch for use in the same. The debugging circuit includes a debugging port, a plurality of microprocessor sockets each adapted to receive a microprocessor, and a plurality of switches corresponding to a respective microprocessor socket. The plurality of microprocessor sockets are adapted to form a serial signal path, and each of the switches is capable of automatically detecting whether a microprocessor is present in the corresponding microprocessor socket. If a microprocessor is present, the switch is automatically configured to include the microprocessor within the signal path, and if the microprocessor is not present, the switch is automatically configured so that the signal path bypasses that microprocessor socket.

System and method for debugging multiprocessor systems

A memory system for a processor-based computing system. The memory system has a number of memory modules and a logic unit. The logic unit examines data to be stored in the memory modules and calculates parity data. It then distributes the input data and the parity data among the memory modules.

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Lago Vista, TX, United States of America

Martin McAfee