Silicon Graphics, Incorporated

Silicon Graphics International Corporation

D.e. Shaw Research, LLC

Lucata Corporation

Martin M Deneroff

Steven C Miller

David Edward McCracken

Gregory Michael Thorson

Curt F Schimmel

Randal Steven Passint

Charles E Leiserson

Bradley C Kuszmaul

Yuval Koren

Givargis George Kaldani

Krste Asanovic

Larry Rudolph

Michael Brian Galles

John Keen

David E Shaw

Kenneth C Yeager

John K Salmon

Ron Dror

David Leo McCall

Kenneth M Sarocky

Richard H Larson

Swami Venkataraman

Lixin Zhang

Scott David Johnson

John B Carter

Stephen Allen Whitney

Steve Dean

John Brennan

Michael Brown

Michael E Anderson

Kumar Venkatasubramaniam

Steven Hein

David Alexander

John R Carlson

Richard T Ingebritson

Robert W Cutler

Timothy S McCann

John Mashey

Russell Jay Anderson

Richard G Bahr

Swaminatham Venkataraman

Michael Parker

Kim Gustafson

Dave Parry

A method of performing diadic operations in a processor is provided that includes receiving a first request packet initiating a read operation from a first memory address in the first request packet, and executing a first operation in the first request packet once the read request is completed. Also, the method includes generating a second request packet at a second memory address by combining the results of the first operation with the unused information in the first request packet. Furthermore, the method includes sending the second request packet to the Memory-Side Processor (MSP). When the MSP receives the second request, the MSP checks to determine if a write operation is requested and writes data to the second memory address, if a read operation is requested, the MSP reads data from the second memory address.

Diadic memory operations and expanded memory frontend operations

A computation system for computing interactions in a multiple-body simulation includes an array of processing modules arranged into one or more serially interconnected processing groups of the processing modules. Each of the processing modules includes storage for data elements and includes circuitry for performing pairwise computations between data elements each associated with a spatial location. Each of the pairwise computations makes use of a data element from the storage of the processing module and a data element passing through the serially interconnected processing modules. Each of the processing modules includes circuitry for selecting the pairs of data elements according to separations between spatial locations associated with the data elements.

Parallel computer architecture for computation of particle interactions

A parallel processing system for computing particle interactions includes a plurality of computation nodes arranged according to a geometric partitioning of a simulation volume. Each computation node has storage for particle data. This particle data is associated with particles in a region of the geometrically partitioned simulation volume. The parallel processing system also includes a communication system having links interconnecting the computation nodes. Each of the computation nodes includes a processor subsystem. These processor subsystems cooperate to coordinate computation of the particle interactions in a distributed manner.

Parallel processing system for computing particle interactions

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Network topology for a scalable multiprocessor system

In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.

Method for performing cache coherency in a computer system

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

System and method for performing memory operations in a computing system

A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Multiprocessor node controller circuit and method

In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Cache coherency is performed on appropriate caches in the computing system in accordance with the selected one of the plurality of coherency protocols. For a second memory transaction, another selection is made of the plurality of coherency protocols. The selected one of the coherency protocols for the second memory transaction may be the same as or different from the selected one of the plurality of coherency protocols for the first memory transaction.

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

A computer system () includes a bus controller (), a bus (), a plurality of processing devices () and a plurality of enabling switches (). Each enabling switch () corresponds to a separate one of the processing devices (). Each processing device () sends an access request () to arbitration logic () in the bus controller (), requesting access to the bus (). The arbitration logic () selects one of the access requests () according to a priority protocol. The arbitration logic () generates a control signal () associated with the selected access request (). The control signal () is provided to the enabling switch () corresponding to the processing device () that sent the selected access request (). The enabling switch () enables access to the bus () for the processing device () in response to the control signal (). In this manner, the computer system () can limit a number of processing devices () having access to the bus () in order to control a load on the bus ().

System and method for providing access to a bus

An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

System and method for performing address translation in a computer system

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Oakhurst, NJ, United States of America

Martin M Deneroff