Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Martin Lueker-Boden

Won Ho Choi

Tung Thanh Hoang

Wen Ma

Pi-Feng Chiu

Lunkai Zhang

Minghai Qin

Anand Kulkarni

Mohammad Reza Mahmoodi

Rasmus Madsen

Raj K Ramanujan

Daniel Lee Helmick

Ward M Parkinson

Dejan Vucinic

Qingbo Wang

Yongjune Kim

Gerrit Jan Hemink

Zvonimir Z Bandic

James E O'Toole

Nathan Franklin

Mark William Branstad

Mitchell Robert Fream

Adarsha Balaji

Zahra Fahimi

Mark Myran

Christoffer Holm Kjølbæk

When a memory system supports different read modes with different read latencies, such as reference read and self-referenced read, read data conflicts can occur for data returned from the memory cells in response to the issued read commands. To support such mixed read modes, embodiments for the memory controller can include separate queues for fast read commands and slow read commands and coordinate the issuing of the two command types. A mixed read coordinator can track issued slow read commands and determine whether a fast read command can be issued. The issued commands are ordered such that they are correctly associated with the read data returned from the memory cells.

Supporting mixed read in non-volatile memory controller

A bypass buffer stores codewords that have been identified as worn out codewords due to stuck-at-failure bit errors and/or other endurance failures. A controller of a data storage device monitors the number of worn out bits of a codeword stored by a memory device of the data storage device. If the number of worn out bits of the codeword exceeds a threshold number of worn out bits, data associated with the codeword is corrected and stored in the bypass buffer. The memory address associated with the codeword is also stored in the bypass buffer and associated with the corrected codeword.

Bypass buffer for worn out codewords

A decryption engine can decrypt encrypted data read from a physical address in a memory of a data storage device. To decrypt the data, the decryption engine can use a tweak value that is generated from a logical address associated with the physical address. To reduce latency, the tweak value can be generated in parallel with the translation of the logical address to the physical address. The tweak value can be stored in a tweak buffer in the decryption engine until needed and can be indexed by a tag associated with a process in a host that is requesting the data. The tweak buffer can use static random-access memory (SRAM) or a content-addressable memory (CAM), for example. Other embodiments are provided.

Data storage device and method for hiding tweak generation latency

Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.

Non-volatile cross-bar memory with on-chip processing circuitry

A mesh network-on-a-chip (NOC) with heterogenous routers for use with homogenous processing elements. Some of the routers are configured differently from other routers to interface more efficiently with particular physical resources that the processing elements require, such as particular input/output or memory devices. For example, one router is configured for use with the Peripheral Component Interconnect Express (PCIe) protocol, whereas another router is configured for use with the InterLaken communication protocol. Still further, the overall system is configured so that the various physical resources are physically adjacent to the particular router that is designed to access the resource to help ensure fair access by each processing element of the NOC to the particular resources that are required. The NOC may be part of a large manycore system on field programmable gate array (FPGA). The methods and apparatus described herein are generally applicable to all system-on-a-chip (SOC) designs.

Mesh network-on-a-chip (NOC) with heterogeneous routers

Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.

Memory controller support for mixed read

Systems and methods disclosed herein provide for reducing noise on an data signal at receiving devices. Systems and methods disclosed herein are suited for opening a data eye by reducing noise, such as inter-symbol interference. An example of the systems and methods disclosed herein include a first equalization circuit that receives an input data signal and applies amplification to the input data signal, and a second equalization that adjusts a first pulse of the first compensated data signal based on a subset of pulses that preceded the first pulse in the first compensated data signal. In an illustrative example, the first equalization circuit can be provided as a continuous time linear equalization (CTLE) that apply a fixed boost and adjustable gain to the input data signal, and the second equalization circuit can be provided as a multi-path decision feedback equalization (DFE).

Data receiver design in DDR memory interfaces

A control circuit for a non-volatile memory array includes an interface to receive requests, a common request queue connected to the interface and a common request buffer connected to the common request queue. The common request buffer is configured to receive the requests from the common request queue in their received order and buffer unfinished requests directed to memory addresses such that for any address in the non-volatile memory array no more than one unfinished request is in the common request buffer.

Memory controller with common request buffer

Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on first transistors operating in respective triode regions. The second current compensates for process, voltage, and temperature variations in the first current at a node. According to some examples, the second current is also generated based on second transistors operating in respective saturation regions. The first current may be generated using a forward biased PN junction diode.

Current reference circuit with process, voltage, and wide-range temperature compensation

A data storage device has a controller, a decryption engine, and a memory storing encrypted data. Instead of using the decryption engine to generate a tweak value needed to decrypt the encrypted data, the tweak value is generated by the controller while the controller is waiting for the encrypted data to be read from the memory. This hides the latency to compute the tweak value in the latency to read the encrypted data from the memory.

Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process variations. Furthermore, disclosed herein is ZQ calibration method that provides for calibrating of the impedance of each of an on-die termination, a pull-up driver, and a pull-down driver using a single calibration circuit.

ZQ calibration circuit and method for memory interfaces

A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors, dropout for inputs can be implemented to reduce overfitting by the neural network.

Dropout in neutral networks using threshold switching selectors in non-volatile memories

Systems and methods are provided for generating a stable DC reference voltage that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners using complimentary metal-on-semiconductor field-effect transistors (MOSFETS). In an example implementation, a reference voltage generator circuit is provided that includes complimentary MOSFETs including a first complimentary MOSFET connected to a first node and having a first threshold voltage, and a second complimentary MOSFET connected to a second node and having a second threshold voltage that is greater than the first threshold voltage. The reference voltage generator circuit feeds the first node a first current based on mirroring a second current at the second node and outputs a stable DC reference voltage based on the first and second complimentary MOSFETs and configured operating in respective saturation regions.

Low line-sensitivity and process-portable reference voltage generator circuit

Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of the array for the multiplication of the input with the weight. To perform a multiply and accumulate operation, the results of the multiplications are accumulated by adders connected to sense amplifiers along the bit lines of the array. The adders can be configured to multiple levels of precision, so that the same structure can accommodate weights and activations of 8-bit, 4-bit, and 2-bit precision.

Multi-precision digital compute-in-memory deep neural network engine for flexible and energy efficient inferencing

An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

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Fremont, CA, United States of America

Martin Lueker-Boden