Altera Corporation

Intel Corporation

Alter Corporation

Martin Langhammer

Keone Streicher

Gregg William Baeckler

Chiao Kai Hwang

Gregory W Starr

Sergey Vladimirovich Gribok

Juju Joyce

David Edward Jefferson

Bogdan Mihai Pasca

Nitin Prasad

Yi-Wen Lin

Volker Mauer

Kumara Tharmalingam

Dongdong Chen

Leon Zheng

Hyun Mo Yi

Simon Peter Finn

Bogdan Pasca

Kwan Yee Martin Lee

Peng T Li

Srinivas T Reddy

Steven Perry

Triet M Nguyen

Sami Mumtaz

Jason R Bergendahl

David Lewis

Paul Metzgen

Henry Y Lui

Suleyman Sirri Demirsoy

Haiyun Yang

Wai-Bor Leung

Orang Azgomi

William Hwang

David James Shippy

Scott J Weber

Divya Vijayaraghavan

Ali H Burney

Greg W Starr

Alejandro Diaz-Manero

Shawn Nicholl

Andrei-Mihai Hagiescu-Miriste

Jeffrey Eastlack

Kevin Hurd

Michael David Hutton

Alexander F Heinecke

Mahesh A Iyer

Jawad Basit Khan

Eriko Nurvitadhi

Richard L Coulson

Ravi Prakash Gutala

Dipankar Das

James G Schleicher

Jung Ko

Dana How

Jon M Long

Aravind Raghavendra Dasu

Albert Fazio

Chuck Rumbolt

Wally Haas

Ilya K Ganusov

Masashi Shimanouchi

Richard Yuan

Kulwinder Singh Dhanoa

Trevis Chandler

Lei Xu

Tomasz Czajkowski

James G Schleicher, Ii

Tim Michael Vanderhoek

Dmitry Nikolai Denisenko

Robert L Pelt

Sasikanth Avancha

Neil Kenneth Thorne

Benjamin Thomas Cope

Guy R Schlacter

Matthew I Adiletta

Richard Maiden

Kellie Marks

Sudarshan Srinivasan

Duncan Moss

Theo Drane

Gregory R Steinke

Gregory Steinke

Jonah Graham

Klaus Engelhardt

Bernd Neidermeier

Jeffery Christopher Chromczak

Robert Cottrell

Kwan Yee Lee

Cheng Wang

Andrei Hagiescu

Terence Magee

Daniel Elphick

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

FPGA specialist processing block for machine learning

The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.

Vector processor architectures

Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.

Rank-based dot product circuitry

A digital signal processing (DSP) block includes a plurality of multipliers and a summation block separate from the plurality of multipliers. The DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers. Additionally, the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value, generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values, and generating a second product of the second multiplication operation by adding, via the summation block, the plurality of subproducts.

High precision decomposable DSP entity

An integrated circuit device includes multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values. Each column of the plurality of columns includes one or more subproducts of a plurality of subproducts. The integrated circuit device also includes adder circuitry configured to determine a plurality of sums, each sum being a sum of one column of the plurality of columns. A first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value and second value that are associated with the first column and a third value associated with a second column of the plurality of columns that differs from the first column. The third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns.

Systems and methods for low latency modular multiplication

A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.

Programmable integrated circuit underlay

Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.

Efficient dual-path floating-point arithmetic operators

An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Integrated circuits with machine learning extensions

The present disclosure relates generally to techniques for adjusting the number representation (e.g., format) of a variable before and/or after performing one or more arithmetic operations on the variable. In particular, the present disclosure relates to scaling the range of a variable to a suitable representation based on available hardware (e.g., hard logic) in an integrated circuit device. For example, an input in a first number format (e.g., bfloat16) may be scaled to a second number format (e.g., half-precision floating-point) so that circuitry implemented to receive inputs in the second number format may perform one or more arithmetic operations on the input. Further, the output produced by the circuitry may be scaled back to the first number format. Accordingly, arithmetic operations, such as a dot-product, performed in a first format may be emulated by scaling the inputs to and/or the outputs from arithmetic operations performed in another format.

Floating-point dynamic range expansion

Systems and methods include arithmetic circuitry that generates a floating-point mantissa and includes a propagation network that calculates the floating-point mantissa based on input bits. The systems and methods also include rounding circuitry that rounds the floating-point mantissa. The rounding circuitry includes a multiplexer at a rounding location for the floating-point mantissa that selectively inputs a first input bit of the input bits or a rounding bit. The rounding circuitry also includes an OR gate that ORs a second input bit of the input bits with the rounding bit. Moreover, the second input bit is a less significant bit than the first input bit.

Rounding circuitry for floating-point mantissas

Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Folded integer multiplication for field-programmable gate arrays

The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).

Circuitry for high-bandwidth, low-latency machine learning

The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Implementing large multipliers in tensor arrays

An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

Accelerator architecture on a programmable platform

Growing community of inventors

Salisbury, United Kingdom

Martin Langhammer