Ams Ag

Austriamicrosystems Ag

International Business Machines Corporation

Martin Knaipp

Georg Röhrer

Jong Mun Park

Georg Roehrer

Rainer Minixhofer

Steven H Voldman

James Albert Slinkman

Martin Schrems

Michael Joseph Zierak

Natalie Barbara Feilchenfeld

Richard A Phelps

Max Gerald Levy

BethAnn Rainey

Hubert Enichlmair

Bernhard Löffler

Bernard Loeffler

Jong-Mun Park

The Schottky barrier diode comprises a semiconductor body with a main surface, a doped region and a further doped region of the semiconductor body, which extend to the main surface, the doped region and the further doped region having opposite types of electric conductivity, a subregion and a further subregion of the further doped region, the subregions being contiguous with one another, the further subregion comprising a higher doping concentration than the subregion, a silicide layer on the main surface, the silicide layer forming an interface with the doped region, an electric contact on the doped region, and a further electric contact electrically connecting the further doped region with the silicide layer.

Schottky barrier diode with improved Schottky contact for high voltages

The field effect transistor device comprises a substrate () of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact () on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact () on the body contact region, and a gate electrode layer () partially overlapping the body well. A portion (*) of the gate electrode layer () is present between the source contact () and the body contact ().

Field effect transistor device with separate source and body contacts and method of producing the device

The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.

Method of producing a high-voltage semiconductor drift device

The semiconductor drift device comprises a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, a drain region of the first type of conductivity at the surface of the substrate, a plurality of source regions of the first type of conductivity in shallow wells of the first type of conductivity at the periphery of the deep well of the first type, and a deep well or a plurality of deep wells of an opposite second type of electrical conductivity provided for a plurality of gate regions at the periphery of the deep well of the first type. The gate regions are formed by shallow wells of the second type of electrical conductivity, which are arranged in the deep well of the second type between the shallow wells of the first type.

High-voltage semiconductor device and method of producing the same

The high-voltage transistor device comprises a semiconductor substrate () with a source region () of a first type of electrical conductivity, a body region () including a channel region () of a second type of electrical conductivity opposite to the first type of conductivity, a drift region () of the first type of conductivity, and a drain region () of the first type of conductivity extending longitudinally in striplike fashion from the channel region () to the drain region () and laterally confined by isolation regions (). The drift region () comprises a doping of the first type of conductivity and includes an additional region () with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (). The drift region depth and the additional region depth do not exceed the maximal depth () of the isolation regions ().

Method of producing a high-voltage transistor

The high-voltage transistor device has a p-type semiconductor substrate that is furnished with a p-type epitaxial layer. A well and a body region are located in the epitaxial layer. A source region is arranged in the body region, and a drain region is arranged in the well. A channel region is located in the body region between the well and the source region. A gate electrode is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.

High-voltage transistor device and production method

High-voltage field-effect transistor and method of making the same

A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

High-voltage transistor and component containing the latter

A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Asymmetric high-voltage JFET and manufacturing process

A body region () with a first type of electric conductivity is arranged at the upper surface () of a substrate () in a well (), wherein a portion of the well that is not occupied by the body region has a second type of conductivity opposite the first type of conductivity. At the upper surface, a source region is arranged in the body region and a drain region is arranged in the well at a distance from the body region; the source region and the drain region both have the second type of conductivity. The body region is arranged underneath a surface area of the upper surface that has a border () with opposing first border sides (). The well has a varying depth in the substrate. The depth of the well is smaller underneath the first border sides of the body region than in a portion of the body region that is spaced apart from the first border sides.

The p-channel LDMOS transistor comprises a semiconductor substrate (), an n well () of n-type conductivity in the substrate, and a p well () of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region () of p-type conductivity is arranged in the p well, and a source region () of p-type conductivity is arranged in the n well. A gate dielectric () is arranged on the substrate, and a gate electrode () is arranged on the gate dielectric. A body contact region () of n-type conductivity is arranged in the n well. A p implant region () is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.

P-channel LDMOS transistor and method of producing a p-channel LDMOS transistor

A semiconductor body () comprises a connecting lead () for contacting a semiconductor area (). The conductivity S per unit length of the connecting lead () changes from a first value SW to a second value S. The semiconductor area () is electrically conductively connected to the connecting lead ().

Semiconductor body and method for the design of a semiconductor body with a connecting line

A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation

A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.

High-voltage transistor with improved high stride performance

A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate () of a second conductivity type, with a source (), a drain (), and a gate electrode () above a channel region (KN, KP) formed between the source and the drain, wherein several staggered and nested wells () of the same conductivity type extend from the source () or the drain () into the substrate () and wherein the doping concentration (log c) of the wells essentially decreases and is smoothed from the substrate surface with increasing depth (T) and also laterally. In this way, field-strength increases and also unintentional breakdown are prevented. Furthermore, a production method is specified.

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Unterpremstätten, Austria

Martin Knaipp