Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies Austria Ag

Qimonda Ag

Seimens Aktiengesellschaft

Martin Kerber

Uwe Wahl

Udo Schwalke

Matthias Stecher

Dietrich Widmann

Jens-Peer Stengl

Andreas Vom Felde

Roland Thewes

Emmerich Bertagnolli

Helmut Klose

Reinhard Mahnkopf

Michael Beck

Peter Lahnor

Alexander Gschwandtner

Andreas Grassl

Alexander Mattheus

Thomas Pompl

Barbara Fr&ouml;schle

Gudrun Innertsberger

Nikolaos Hatzopoulos

One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Semiconductor structure including guard ring

A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Signal transmission arrangement

Techniques disclosed herein stress a dielectric layer until a pre-catastrophic, stress induced leakage current (SILC) condition is detected. When the pre-catastrophic SILC condition is detected, the stress is removed to prevent catastrophic failure of the dielectric and its associated device. Because these techniques prevent catastrophic failure of the dielectric layer, engineers can carry out physical failure analysis of the device, which is now known to have some type of defect due to detection of the pre-catastrophic SILC condition. In this way, the techniques disclosed herein allow engineers to more quickly determine an underlying cause of a defect so that yields can be kept at optimal levels.

Detection of pre-catastrophic, stress induced leakage current conditions for dielectric layers

One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material.

High voltage semiconductor devices and methods of forming the same

In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Method and apparatus for reducing charge trapping in high-k dielectric material

A system including a tester configured to measure a first current from a first die of neighboring dice and a second current from a second die of the neighboring dice. The tester is configured to compare the first current to the second current to detect damage in the neighboring dice.

System that detects damage in adjacent dice

The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

Procedure for arranging chips of a first substrate on a second substrate

A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with a sacrificial layer. A selective back-etching of the sacrificial layer is carried out, such that the cavities adjacent to the surface remain filled with the sacrificial layer. A second insulating layer is applied directly to the first insulating layer and, in a subsequent method step, a conducting layer is applied to the second insulating layer.

Method for the elimination of the effects of defects on wafers

Test arrangement having chips of a first substrate on a second substrate and chips of the second substrate on a third substrate

A semiconductor wafer includes a dielectric test structure including a voltage line, a control line, and a plurality of test devices connected in parallel to the voltage line and the control line. Each test device includes a voltage-controlled resistor connected to the control line and a dielectric device, the dielectric device being connected to the voltage line via the voltage-controlled resistor. A method for dielectric reliability testing and forming an integrated circuit product is also provided, as is a wafer with a control voltage pad and an integrated circuit product.

Semiconductor wafer having a dielectric reliability test structure, integrated circuit product and test method

The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.

Electronic switching circuit, switching circuit test arrangement and method for determining the operativeness of an electronic switching circuit

Fluorine is deposited on a semiconductor substrate surface according to a novel process. A semiconductor substrate is placed in a reaction chamber and the substrate surface is wetted with water and/or alcohol. A compound containing fluorine is led to the substrate surface, so that a cleaned semiconductor surface covered with fluorine is produced, and the compound containing fluorine is removed from the reaction chamber. The cleaned semiconductor surface covered with fluorine is then wetted with a mixture containing at least 10% by volume of water and at least 10% by volume of alcohol, for producing a cleaned semiconductor surface covered with a predetermined amount of fluorine. The predetermined amount of fluorine is lower the higher a proportion of water in the mixture is chosen to be. Then, the water and the alcohol are removed from the semiconductor surface.

Growing community of inventors

Munich, Germany

Martin Kerber