Cypress Semiconductor Corporation

Martin Jonathon Steadman

David Brian Rees

A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

Pass transistor capacitive coupling control circuit

A circuit comprising a main memory array with a block of columns per data I/O, a main read/write block per block of columns, one or more spare memory columns, a bad address detector circuit per spare column, and a read/write block per spare column. A spare column may replace a defective column or cell in any of the blocks of columns. The spare column may be read from/written to via the main read/write block of the column it is replacing, or via its own dedicated read/write block to improve access times. The bad address detector can be configured with programmable elements to produce a control signal when the address of a defective memory element (cell or column) is applied. This signal is then used to disable the defective memory element (and read/write block) and enable a spare column (and read/write block) in its place. The present invention also comprises a recovery circuit on the local data lines (multiplexed to the addressed bitlines). The recovery circuit in the block with the defective column is activated during a spare access. This allows the memory to be tolerant of some of the faults normally combated with column disconnect fuses without the use of such fuses. The present invention also comprises a logic circuit that utilizes a signal synchronized to the address signals to improve the speed of operation of the redundancy scheme.

Redundancy scheme providing improvements in redundant circuit access

A bidirectional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2, involves controlling the voltage V1 on gate of MN1 using a gate node N1 that is coupled to supply voltage VCC under the control of two transistor pairs MN3, MN4 and MP3, MP4 that sense the voltages on IO1 and IO2, and an inverter pair MP2, MN2 having a voltage signal ENB input on its gates. If the voltages on nodes IO1 and IO2 both go high, MP3 and MP4 tend to turn OFF dropping gate voltage V1, via MP2, below VCC and tending to turn MN1 OFF. Leakage from node N1 in such event occurs through a small current bleed network formed by three transistors MN6, MN7, and MN8.

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London, United Kingdom

Martin Jonathon Steadman