Hewlett-packard Company

Institute for the Development of Emerging Architecture L.l.c.

Martin J Whittaker

Millind Mittal

Gary N Hammond

Jerome C Huck

James M Hull

Alejandro Quiroz

Michael R Morrell

Vishal Malik

Atomic memory operations are provided by using exportable &ldquo;fetch and add&rdquo; instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-32 lock check enable bit (LC) that when set to &ldquo;1&rdquo;, causes an IA-32 atomic memory reference to raise an IA-32 intercept lock fault. An IA-32 intercept lock fault handler branches to appropriate code to atomically emulate the instruction. Furthermore, the present invention defines an exportable fetch and add (FETCHADD) instruction that reads a memory location indexed by a first register, places the contents read from the memory location into a second register, increments the value read from the memory location, and stores the sum back to the memory location. Associated with each virtual memory page is a memory attribute that can assume a state of &ldquo;cacheable using a write-back policy&rdquo; (WB), &ldquo;uncacheable&rdquo; (UC), or &ldquo;uncacheable and exportable&rdquo; (UCE). When a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to WB, the FETCHADD is atomically executed by the CPU by obtaining exclusive use of the cache line containing the memory location. However, when a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to UCE, the FETCHADD is atomically executed by exporting the FETCHADD instruction to a centralized location, such as a memory controller.

COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK

A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.

Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically

A data processing system having a central processing unit for executing instructions stored in a memory, a plurality of peripheral ports at a plurality of physical locations, and a routing network for coupling the central processing unit to the peripheral ports. The routing network has a network storage device for storing information relating to the physical locations of the ports, and a controller responsive to a command for reporting such information. Peripherals used in the data processing system preferably have a peripheral storage device for storing information relating to characteristics of the peripherals and a peripheral controller responsive to a command for reporting such information.

System for storing physical locations of all ports specified in terms of

Growing community of inventors

Cupertino, CA, United States of America

Martin J Whittaker