Wang Laboratories, Inc.

Raytheon Company

Teradyne, Inc.

Robert D. Becker

Anthony S. Fong

Martin J. Schwartz

Janis Delmonte

Martin J Schwartz

Robert D Becker

Kevin H Curcuru

Gerald F Muething, Jr

Anthony S Fong

Richard W Coyle

H Frank Howes

John A Saba

Richard Tank-Kong

Richard F Giunta

Kenneth J Eng

Richard J Edry

Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signal are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circuit chip. To allow this level of integration without degrading timing accuracy, a series of design techniques are employed. These techniques include the use of guard rings and guard layers, placement of circuit elements in relation to the guard rings and guard layers, separate signal traces for power and ground for each channel, and circuit designs that allow the voltage across a filter capacitor to define a correction signal. Another feature of the disclosed embodiment is a fine delay element design that can be controlled for delay variations and incorporates calibration features. A further disclosed feature is circuitry that allows the tester to have a short refire recovery time.

Tester with fast refire recovery time

A prefetch unit includes a Branch history table for providing an indication of an occurrence of a Branch instruction having a Target Address that was previously taken. A plurality of Branch mark bits are stored in an instruction queue, on a half word basis, in conjunction with a double word of instruction data that is prefetched from an instruction cache. The Branch Target Address is employed to redirect instruction prefetching. The Branch Target Address is also pipelined and follows the associated Branch instruction through an instruction pipeline. The prefetch unit includes circuitry for automatically self-filling the instruction pipeline. During a Fetch stage a previously generated Virtual Effective Address is applied to a translation buffer to generate a physical address which is used to access a data cache. The translation buffer includes a first and a second translation buffer, with the first translation buffer being a reduced subset of the second. The first translation buffer is probed, during a Generate stage, to prefetch, if possible, the required operand. The prefetch unit further provides 24-bit or 31-bit effective address generation on an instruction by instruction basis.

CPU having pipelined instruction unit and effective address calculation

A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus. The reading logic includes read request receiving and buffer logic having a plurality of storage locations for storing received read requests and associated read addresses prior to the execution of the read requests. The memory control unit further has logic for comparing a received read address to write addresses stored in the write address buffer, the comparing logic having an output for indicating, when asserted, the occurence of the reception of a read address having a value within a predetermined range of values of one of the stored write addresses.

Memory control unit with selective execution of queued read and write

A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus. The dual functionality of the first group of signal lines eliminates the requirement for separate and dedicated command/ID and data signal line paths and associated driving and receiving circuit elements.

System bus having multiplexed command/ID and data

A system having a CPU, a main memory and a bus. A cache memory couples the CPU to the bus and is provided with circuitry to indicate the status of a data unit stored within the cache memory. One status indication indicates whether the contents of a storage position have been modified (dirty) since those contents were received from main memory. Another status indication indicates whether the contents of the storage position exist within another cache memory (shared). Each cache includes a bus monitor that monitors bus transactions. When data is read from system memory by a first cache a second cache determines if the data is shared. If yes, the second cache asserts a bus hold line and determines if the shared data is dirty. If yes, the second cache drives the corresponding data to the bus for storage within the first cache. For a system memory write, the second cache latches the data and determines if the data is shared. If yes, the second cache replaces its copy of the data with that latched from the bus. As such, no cache 'valid' status bits are required in that each cache is assured of having the most current version of data.

Multi-processor system with cache memories

Apparatus for executing a conditional branch instruction in a pipelined processing unit which has an instruction queue for storing an instruction stream, address generating apparatus connected to the head of the instruction queue for generating and retaining an address defined in the portion of the instruction stream presently at the head of the instruction queue, and instruction interpretation apparatus which is also connected to the head of the instruction queue for receiving and interpreting an instruction at the head of the instruction queue. A conditional branch instruction which is presently at the head of the instruction queue is executed by first performing a dispatch operation in a first cycle which is the last cycle of execution of the instruction preceding the conditional branch instruction in the instruction queue. The dispatch operation sets up the execution of the instruction at the head of the instruction queue. One result of the dispatch operation is the generation of the address for the target instruction specified in the branch instruction. Thereupon, in an immediately following second cycle, a conditional fetch operation and a test operation are performed. The conditional fetch operation provides the address for the target instruction to the processing unit's memory. The test operation determines whether the branch is to be taken. If the branch is not to be taken, the target instruction is not loaded into the instruction queue, the cycle is extended, and a dispatch operation is performed in the extended cycle. If the branch is to be taken, the target instruction is loaded into the head of the instruction queue in the second cycle. Finally, when the branch is taken, the dispatch operation is performed in an immediately following third cycle.

Apparatus and method for executing a conditional branch instruction

A system console 30 is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays 16-22. The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array 40, one of which is disposed upon each of the memory boards 12 and 14 and also upon a memory controlling unit 26, the memory logic arrays being coupled together by a bit serial scan bus 42. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all subsequent memory boards.

Memory diagnostic apparatus and method

A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether the contents of a storage position have been modified since those contents were received from main memory and another indicates whether the contents of the storage position may be present elsewhere memory means. Control means are provided to assure that when a data unit from a CPU is received and stored in the CPU's associated cache memory means, which data unit is indicated as being also stored in a cache memory means associated with another CPU, such CPU data unit is also written into main memory means. During that process, other cache memory means monitor the bus means and update its corresponding data unit. Bus monitor means are provided and monitor all writes to main memory and reads from main memory to aid in the assurance of system-wide data integrity.

A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that individual bytes of each word are aligned in columns. Each column of bytes is addressable independently of the other byte columns via adders. A most significant bit portion of a memory location address is fed into a first input of column adders and the output of a first decoder circuit is fed into a second input of the adders for address incrementing within one memory cycle. A second decoder circuit generates a separate read or write enable line to each column of bytes. Both decoders are controlled by a least significant bit portion of the memory address and reference word byte size codes. A bi-directional multiplexer rearranges the order of the bytes so they appear in the proper order at the memory interface.

Growing community of inventors

Worcester, MA, United States of America

Martin J Schwartz