Texas Instruments Corporation

Martin J Izzard

Baher S Haroun

Srinath Hosur

Nirmal Chindhu Warke

Marco Corsi

Siraj Akhtar

Swaminathan Sankaran

David Barry Scott

Hassan Omar Ali

Jing-Fei Ren

Venugopal Gopinathan

Gitty N Nasserbakht

Brad Kramer

Richard Mark Prentice

Randall J Landry

Ah-Lyan Yee

E Ajith Amerasekepa

Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. In one embodiment, a networking device includes an input port circuit having a transmitter circuit coupled one or more transmitter antennas, wherein the input port circuit transmits a data packet to a first output port circuit using millimeter wave signals. The networking device includes output port circuits including at least the first output port circuit, each of the output port circuits having a receiver circuit coupled to one or more receiver antennas. The networking device includes a beamforming circuit coupled to the one or more transmitter antennas of the input port circuit, wherein the beamforming circuit causes the one or more transmitter antennas to transmit an antenna beam directed at the one or more receiver antennas of the first output port circuit.

Wireless chip-to-chip switching

Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.

Conventional routers employ a wired backplane that employs 'long reach' serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.

Wireless router system

The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device ( ) includes a transmit serializer ( ), a transmit output buffer ( ), a first phase interpolator ( ), a phase locked loop ( ), a second phase interpolator ( ), a receive deserializer ( ), a receive input buffer ( ), and phase adjust logic ( ). The PLL ( ) generates a timing signal in accordance with a reference clock signal ( ). In one mode of operation, the transmit serializer ( ) transmits data for output through the transmit output buffer ( ) in accordance with the timing signal generated by the PLL ( ). In another mode of operation, the phase interpolator ( ) accepts as input the timing signal generated by the PLL ( ). The phase interpolator ( ) then generates an altered timing signal which the transmit serializer ( ) uses to transmits data for output through the transmit output buffer ( ) asynchronously from the timing signal of the receive deserializer ( ).

Self test of an electronic device

An output driver device (,) includes a first output transistor (,) and a second output transistor (,) coupled to a bias transistor (,). The bias transistor (,) is coupled to a ground potential. The first output transistor (,) is coupled to a first output pad (,) and the second output transistor (,) is coupled to a second output pad (,). The output driver device (,) has a direct non-metal path to ground potential from either the first output pad (,) or the second output pad (,). In this manner, an electrostatic discharge device on either the first output pad (,) or the second output pad (,) can be absorbed through the first output transistor (,) or the second output transistor (,), respectively, and through the bias transistor (,) without damaging the output driver device (,).

Output driver device with electrostatic discharge protection

A priority encoder circuit (,) is provided. The priority encoder circuit (,) includes a plurality of inputs (,) and outputs (,). The number of inputs (,) equals the number of outputs (,), and each input (,) corresponds to one output. Each input (,) receives a signal that indicates whether the input (,) has been selected. The priority encoder circuit (,) also includes circuitry (,) that generates a signal at the output (,) corresponding to the input (,) having the highest priority that receives the selection signal.

Priority encoder circuit

A packet switch (26) has N digital input ports (28) each of bandwidth B for receiving data cells including destination addresses for determining output ports, a shared input cache (32), N memory modules (36) of bandwidth N.times.B for buffering, a switch fabric (38), and N digital output ports (40). A digital multiplexer (30) receives each data cell from the input ports (28) and writes it to the shared input cache (32) together with a corresponding port queue number, queue position, and memory module number in response to its destination address so that (1) cells having the same queue number are cyclically assigned to different memory modules (36) and (2) cells having the same queue position are cyclically assigned to different memory modules (36). A digital demultiplexer (34) reads each data cell from the shared input cache (32) and writes it to one of the N memory modules (36) according to its assigned memory module number and queue position. Then the switch fabric (38) reads the data cells in each memory module (36) by queue position and writes each to a corresponding output port (40) matching the cell's queue number.

Distributed shared-memory packet switch

An ocular projection display (12) projects an image directly to the eye (26) of the user (10). The focus of the image may be varied to allow for different user profiles or to relieve the stress of maintaining a fixed focus over a prolonged period of time. Optionally, the ocular projection display (12) can include a location and distance sensor (46) for identifying the location of the user's eyes for proper aiming of the image to the eyes of the user and focus detection circuitry (54) to correct for the user's focusing abilities.

Adaptive ocular projection display

An embodiment of the present invention is electronic circuitry for producing an I-phase quadrant pointer (FI) and a Q-phase quadrant pointer (FQ) by sampling a feed clock (IC) and a quadrature feed clock (QC), the circuitry comprises: a first quadrant detector (406, FIG. 5) for producing the Q-phase quadrant pointer in response to receipt of the feed clock and input data; a second quadrant detector (408, FIG. 5) for producing the I-phase quadrant pointer in response to receipt of the feed clock and the input data; and wherein the I-phase quadrant pointer and the Q-phase quadrant pointer can be utilized to determine the phase quadrant of the input data.

First-order loop control configuration for a phase-rotator based clock

In an embodiment of the present invention is electronic circuitry for producing a clock signal, and its quadrature, whose phase matches the phase of input data in response to receipt of the input data and a reference clock signal, the circuitry comprises: circuitry for providing the quadrature of the reference clock signal; circuitry for providing a Q-phase quadrant pointer in response to the input data, and the reference clock; circuitry for providing an I-phase quadrant pointer in response to the input data, and the quadrature reference clock; circuitry for providing a phase signal in response to the produced clock, the quadrature of the produced clock and the input data; circuitry for providing a phase-change signal for specifying whether to rotate the phase of the produced clock signal in one direction or the other, the circuitry operable in response to the I-phase quadrant pointer, Q-phase quadrant pointer and the produced clock signal; a first phase rotator for changing the phase of the produced clock in response to the phase-change signal, the I-phase quadrant pointer, the Q-phase quadrant pointer, the reference clock, and the quadrature reference clock; and a second phase rotator for changing the phase of the quadrature of the produced clock in response to the phase-change signal, the I-phase quadrant pointer, the Q-phase quadrant pointer, the reference clock, and the quadrature reference clock.

A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.

Phase detector and method

A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

Growing community of inventors

Dallas, TX, United States of America

Martin J Izzard