Agilent Technologies, Inc.

Martin Heinen

Joachim Moll

Guenther Tietz

Thomas Burger

An integrated circuit (), preferably a field programmable gate array&#x2014;FPGA or an application specific integrated circuit&#x2014;ASIC&#x2014;, comprises a level comparator () for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit () is coupled to the level comparator () for sampling (SAM) the comparator output signal (COS). A bit error test unit () receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Integrated circuit with bit error test capability

For identifying or localizing a serial data stream in a deserialized output provided at a plurality of n output ports (PORT-PORT), a pattern recognition is provided at each one of the plurality of n output ports (PORT-PORT) for recognizing a deserialized identifier pattern corresponding to an identifier pattern within the serial data stream and for detecting a phase of the deserialized identifier pattern in the deserialized output. The phase of the output of each respective port (PORT-PORT) is then shifted in correspondence with the detected phase of the deserialized identifier pattern.

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Bondorf, Germany

Martin Heinen