Spts Technologies Limited

Martin Hanicinec

Oliver James Ansell

Janet Hopkins

David Andrew Tossell

A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Semiconductor wafer dicing process

A method is for plasma etching one or more dicing lanes in a silicon substrate having a backside metal layer attached thereto. The method includes performing a main etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated to produce dicing lanes having scalloped sidewalls, and switching to performing a secondary etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated until the backside metal layer is reached. The amount of silicon removed in one etch step during the secondary etch is half or less than half of the amount of silicon removed in one etch step during the main etch.

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Newport, United Kingdom

Martin Hanicinec