Intel Corporation

Other

Google Inc.

Intel Corparation

Martin Guy Dixon

Vinodh Gopal

Wajdi K Feghali

Gilbert M Wolrich

James D Guilford

Erdinc Ozturk

Srinivas Chennupaty

Shay Gueron

Bret L Toll

Kirk S Yap

Michael E Kounavis

Sean M Gulley

Raghunandan Makaram

Sean Mirkes

Maxim Loktyukhin

Alexandre J Farcy

Konrad K Lai

Ravi Rajwar

Matthew C Merten

Mark C Davis

William Rash

Yazmin A Santiago

Gilbert A Neiger

Scott Dion Rodgers

Rajesh S Parthasarathy

Elmoustapha Ould-Ahmed-Vall

Jason W Brandt

Baiju V Patel

Eric W Mahurin

Mayank Bomb

David L Kreitzer

Mark Jay Charney

Per H Hammarlund

Robert S Chappell

Robert Valentine

Christopher J Hughes

Jesus Corbal

Stephen H Gunther

Milind Baburao Girkar

Prashant Sethi

James B Crossland

Jonathan Cannon Hall

Chris J Newburn

Mark J Buxton

Peter Lachner

James S Coke

Jeffrey G Wiedemeier

Deniz Karakoyunlu

Kahraman D Akdemir

Taraneh Bahrami

Glenn J Hinton

Stephen Anthony Fischer

David B Papworth

Asit K Mallick

David Johnston

George W Cox

Brent Ralph Boswell

Peggy J Irelan

Vijaykumar Balaram Kadgi

Tong Li

Laura A Knauth

Ilhyun Kim

Andrew F Glew

Edward Thomas Grochowski

Barry E Huntley

Jesse R Walker

Ravishankar Iyer

Ernie F Brickell

Jeremy J Shrall

H Peter Anvin

Howard C Herbert

David A Koufaty

Vasudevan Srinivasan

James Paul Held

Li Zhao

Scott H Robinson

Paul Caprioli

Donald K Newell

Rameshkumar G Illikkal

Adriaan Van De Ven

Frank Binns

Leena K Puthiyedath

Sham M Datta

Camron B Rust

Michael Cornaby

Scott D Hahn

John G Holm

Joseph Frank Cihula

Scott P Bobholz

Hermann Gartler

Charles E Dike

Mishali Naik

Erik Hallnor

Larry O Smith

Chinmay Ashok

Omar M Shaikh

David T Mayo

Muawya M Al-Otoom

Edward V Gamsaragan

Don Alan Van Dyke

The technology generally relates to systems and methods for performing in-field testing of processing cores within a system-on-chip (SoC), so as to identify faults, including those associated with silent data corruption. For example, an SoC may contain operational cores and spare cores. An operational core may be selected for testing while a spare core is used to replace the tested core. In addition, a spare core may be used to replace an operational core that has been determined to be corrupted.

Systems and methods for usage of spare cores in connection with in-field tests of operational cores

Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

Techniques for restricted deployment of targeted processor firmware updates

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Rotate instructions that complete execution either without writing or reading flags

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Method and apparatus to process SHA-2 secure hashing algorithm

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Addition instructions with independent carry chains

A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

Processor to perform a bit range isolation instruction

A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Multiplication instruction for which execution completes without writing a carry flag

A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a 'one round' pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Flexible architecture and instruction for advanced encryption standard (AES)

System-on-chip (SoC) to perform a bit range isolation instruction

Growing community of inventors

Portland, OR, United States of America

Martin Guy Dixon