Globalfoundries Inc.

Advanced Micro Devices Corporation

Martin Gerhardt

Ralf Richter

Stefan Flachowsky

Uwe Griebenow

Frank Wirbeleit

Matthias Kessler

Jan Hoentschel

Manfred Horstmann

Roman Boschke

Thomas Feudel

Igor V Peidous

Andy C Wei

Kai Frohberg

Stephan Kronholz

Thorsten E Kammler

Peter Javorka

Markus Lenski

Joerg Hohage

Alban Zaka

Juergen Faul

Martin Trentzsch

Ricardo Pablo Mikalo

David E Brown

Christoph Schwan

Ran Yan

Tom Herrmann

Martin Mazur

Lars Mueller-Meskamp

Markus Forsberg

Damien Angot

Venkata Naga Ranjith Kuma Nelluri

Markus Forseberg

In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

Transistor element with reduced lateral electrical field

A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell

An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.

Heat dissipative element for polysilicon resistor bank

A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof

Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

OPC enlarged dummy electrode to eliminate ski slope at eSiGe

An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Transistor devices with high-k insulation layers

When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes.

Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages

Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).

Methods of forming transistor devices with high-k insulation layers and the resulting devices

By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.

Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation

By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Technique for enhancing transistor performance by transistor specific contact design

When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography

By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

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Dresden, Germany

Martin Gerhardt