Ford Motor Company Limited

Visteon Global Technolgoies, Inc.

Alereon, Inc.

Visteon Corporation

Alerecn, Inc,

Martin G Gravenstein

Samuel James Guido

Rollie Morris Fisher

Silvia E Jaeckel

Raymond Allen Stevens

Vernon R Brethour

Robert L Anderson

Kevin Michael Rishavy

Gary Thomas Bastian

Michael A Vigil

Nirmalendu B Patra

Andrew Probst

Michael Anthony Viigil

Dave Ohmann

Clair A Hardesty

Methods, systems, and apparatuses are described which are capable of mitigating interference between piconets. Devices on a piconet may detect a certain degree of interference. When this interference is deemed as arising from another piconet, the first piconet may cease transmitting on a set of bands while the interfering piconet may continue to transmit on this set of bands. Furthermore, the interfering piconet may cease transmitting on another orthogonal set of bands within the frequency spectrum while the original piconet continues to utilize these bands. Transmission on these sets of bands may be resumed after a predetermined time period. In this manner interference between the two piconets may be minimized.

Methods and apparatuses for reducing interference using frequency division multiple access

Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system including a plurality of memory units which are accessible in parallel, a dynamic memory unit configured to dynamically allocate and deallocate storage space in the memory units, and a plurality of direct memory access (DMA) engines configured to access the memory units in parallel through the memory management subsystem. The system may be implemented in the MAC engine of a device that communicates with other devices via a wireless communication link. This embodiment may store packets in FIFOs within the memory units as elements of linked list data structures that can be joined together without having to move the previously stored data. DMA engines access a context table to obtain DMA channel information that enables them to move data through appropriate DMA channels.

Systems and methods for efficient memory management

A controllerhas an I/O crossover switching network, an optional I/O network expansion, a plurality of serial I/O shifters, a clock generatorand I/O control logic. The I/O crossover-switching networkis also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA)or an optional alternate pathwaywhich uses one of a plurality of parallel pins. The optional alternate pathwaycan be used when pinsare unavailable or to reduce the number of pins on the device. The controller is shown to communicate with an external devicealso having parallel pins. While a single deviceis shown, the external devicecan be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessorof the present invention.

I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control

A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.

Queued port data controller for microprocessor-based engine control applications

An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

A multi-function timer used to perform multiple input timing measurements and generate multiple timed output events on the I/O pins of the apparatus. The multi-function timer comprises a plurality of slots and a compute engine. Each of the slots represents one of a plurality of timing processes. The compute engine includes a micro-sequencer and a processor. The micro-sequencer identifies a current slot and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots. The processor performs the functions of the instructions associated with each current slot. Further, each slot is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input. The multi-function timer is advantageous in that it provides application design flexibility by eliminating the need for dedicated logic for input and output timing functions.

Multi-function timer with shared hardware

A data movement apparatus (10) and method therefor include a register file (14) for storing data in a plurality of addressable locations. A register decoder (18) is connected to the register file (14) to modify addresses to access desired data. During move commands, data is not physically moved in the register file (14), but the register decoder (18) modifies a variable upon receiving the move command to correlate the new logical address to the physical location.

Data movement apparatus and method

A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

Micro-sequencer apparatus and method of combination state machine and

A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.

Growing community of inventors

Nevada City, CA, United States of America

Martin G Gravenstein