Dialog Semiconductor (uk) Limited

Dialog Semiconductor Gmbh

Martin Faerber

Horst Knoedgen

Mark Johnathan Childs

Guillaume De Cremoux

Kemal Ozanoglu

Pier Cavallini

Jens Masuch

Jindrich Svorc

Alessandro Molari

Giulio De Vita

Circuits and methods to achieve a hysteretic buck-boost converter system, separating buck and boost pulses based on monitoring a difference between the output voltage of the buck-boost converter and a reference voltage (error voltage) or alternatively based on monitoring additionally coil current or load current or both currents have been disclosed. The performance of the buck-boost converter can be further improved by using an optional output voltage change block monitoring if the output voltage rises or falls. The buck-boost converter disclosed has a very simple topology without a modulator block, which is regulating the duty cycle and without frequency compensation.

Buck-boost converter using hysteretic control

A switched mode power converter comprising a main inductor and a half bridge for providing an inductor current is described. The power converter comprises a first output power switch for directing the inductor current to a first output port and bypass circuitry for making at least part of the inductor current available for controlling the switching state of at least one of the power switches. Furthermore, the power converter comprises a control unit configured to control the first output power switch such that the inductor current is directed to the first output port within different first time intervals. Furthermore, the bypass circuitry is controlled to make the inductor current available for controlling the switching state of the at least one power switch during a non-overlapping time interval.

Switched power converter with multiple outputs

A multiphase switching converter with a plurality of phase circuits coupled with a common output node is presented. Each phase circuit has a drive signal generator to generate a separate drive signal for a switching element of the respective phase based on a feedback signal from the common output node. Multiple voltage loops with different bandwidths or hysteresis are suggested for a multiphase power converter. In embodiments, this allows a slow phase ('Master') with a big inductor and low switching frequency and one or multiple fast phases ('Slaves') with small inductors and high switching frequency. The Master phase will allow the system to have high efficiency at low output load, while the Slave phase(s) will deliver extra current during load transient and for higher loads.

Multiphase switching converter

A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Dynamic current limit circuit

A time off estimator and an adaptive controller implemented on an integrated circuit to emulate current dependent zero crossing circuitry to permit improved performance of a buck type switching mode power supply. The time off estimator circuit is enhanced by an automatic correction circuit for the timing of a zero crossing where energy to a reference capacitor returns to zero and is turned off awaiting the next cycle where the capacitor is again charged and discharged.

Adaptive low-power zero-cross comparator for discontinuous current mode operated switching mode power supply

Circuits and methods to detect a threshold for entering and leaving a discontinuous current mode of a buck converter have been disclosed. A buck converter is switched to continuous mode if the filtered battery current has reached a defined threshold current I. In order to expedite the transition from DCM mode to CCM mode the time delay between two or more pulses of a current through an inductor is monitored and the buck converter is switched to CCM mode if this time delay is smaller than a defined threshold.

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Munich, Germany

Martin Faerber