Netlogic Microsystems, Inc

Martin Fabry

Michael E Ichiriu

Sanjay Sreenath

Larry A Wall

Ajit Ninan

Minh G Lieu

M Neil N Mammen

A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of, an access operation.

Methods and circuits for limiting bit line leakage current in a content addressable memory (CAM) device

A content addressable memory (CAM) device can include a number of bit line. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit can have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state in response to, and no later than the start of, an access operation.

A method of placing a content addressable memory (CAM) into a low current state is disclosed. The CAM can include at least one storage location that does not store valid data for a compare operation and includes a plurality of CAM cells, each CAM cell having at least two data controllable impedance paths arranged in parallel with one another. The method can include configuring the majority of the CAM cells to store data values that maintain the corresponding at least two data controllable impedance paths in high impedance states.

Methods and circuits for placing unused content addressable memory (CAM) cells into low current states

A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path that is temporarily enabled in response to an activated second control signal and a valid indication that indicates whether or not the corresponding group of CAM cells stores valid data, the valid indication being different than the first and second control signals.

Match line precharge circuits and methods for content addressable memory (CAM) device

A content addressable memory (CAM) device can include a number of match lines, each coupled to a plurality of CAM cells. The CAM device also includes one or more one precharge circuits. Such a precharge circuit can have a first precharge path that couples a match line to a precharge voltage node in response the activation of a first control signal, and a second precharge path that couples the match line to the precharge voltage node in response to the activation of a second control signal. Prior to a compare operation leakage current through the CAM cells can prevented by disabling the precharge paths and isolating the CAM cells from a reference voltage (e.g., ground). The second control signal can be activated after the first control signal in a compare operation.

A content search system for determining whether a plurality of input strings each belonging to any one of a number of different process flows matches one or more of a plurality of regular expressions, including a search circuit for searching the input strings for the regular expressions and a data management unit including a control circuit having an input to receive the plurality of input strings, wherein each input string has an associated flow identification (ID) value, a packet queue having a number of storage locations for storing the input strings, and a flow engine that forwards a selected input string from the packet queue to the search circuit.

Method and apparatus for managing multiple data flows in a content search system

A search engine configured to determine whether an input string including a plurality of input characters matches a regular expression including an inexact pattern including a specified range of instances of pattern characters each belonging to a specified set of characters, the search engine including a microcontroller having an input to receive a microprogram embodying the inexact pattern, a first co-processor coupled to the microcontroller and dedicated to determine whether each input character in a first portion of the input string is a member of the specified set of characters, and a second co-processor coupled to the microcontroller and dedicated to determine whether the number of input characters in the first portion of the input string falls within the specified range.

Search engine having multiple co-processors for performing inexact pattern search operations

A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.

Regular expression searching of packet contents using dedicated search circuits

A content search circuit for determining whether an input string matches one or more of a plurality of regular expressions, the content search circuit including an instruction memory for storing a plurality of microprograms, each microprogram embodying a corresponding one of the regular expressions, a control circuit having an input to receive the input string, and having a number of outputs, and a plurality of search engines, each having a first input coupled to a corresponding output of the control circuit and having a second input coupled to the instruction memory, wherein each search engine is selectable to execute any of the microprograms stored in the instruction memory to search the input string for any of the regular expressions embodied in the microprograms.

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Mountain View, CA, United States of America

Martin Fabry