International Business Machines Corporation

Globalfoundries Inc.

Martin Eckert

Otto Andreas Torreiter

Quintino Lorenzo Trianni

Siegfried Tomaschko

Roland Dieterle

Eckhard Kunigkeit

Thomas Gentner

Roland Frech

Thomas Strach

Dieter F Wendel

Juergen Pille

Christian Zoellin

Alexander Fritsch

Jochen Supper

Jens Kuenzer

Antje Mueller

Tobias Werner

Hubert Harrer

Michael B Kugel

Thomas-Michael Winkel

Matthias Pflanz

Joerg Georg Appinger

Gabriele Kuczera

Marta Junginger

Eberhard Dengler

Nils Schlemminger

Claudio Siviero

Matthias Klein

Markus Helms

Christine Axnix

Thomas Schlipf

Andrew A Turner

Andreas Wagner

Daniel D Sentler

Rainer Dorsch

Manfred Walz

Juergen Probst

Walter Heinrich Lipponer

Frank William Angelotti

Klaus K Kempter

Thomas Buechner

Gary Alan Peterson

Gerhard Zilles

Guenter Mayer

Kenneth Lee Christian

Rohan A Jones

Michael D Campbell

Neil A Malek

Dermot Weldon

Georg Goecke

Markus Ulbricht

Harmut Ulland

Jörg Georg Appinger

The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.

Device for positioning a semiconductor die in a wafer prober

The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

Integrated circuit with optical tunnel

Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.

Stressing integrated circuits using a radiation source

An adjustable load transmitter for adjusting an alignment between a probe card and a bridge beam of a wafer prober, where the probe card is separated from the bridge beam by a gap. The adjustable load transmitter located in the gap, the adjustable load transmitter comprising two rotatable plates adapted for transmitting a load via a load transmission path between the bridge beam and the wafer prober and each comprising two flat, non-parallel contact faces. The adjustable load transmitter removes an angular misalignment between the bridge beam and the set of plates by rotating each of the rotatable plates about a pre-determined adjustment angle such that two angles of inclination are adjusted to zero. The adjustable load transmitter establishes the load transmission path by closing a clearance between the bridge beam and the contact face.

Probe card alignment

A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Functional testing of high-speed serial links

A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.

Content addressable memory with match hit quality indication

The disclosure relates to an adjustable load transmitter for adjusting an alignment between planar members separated from each other by a gap. The load transmitter comprises a set of plates to be received inside the gap, the set comprising two rotatable plates and being adapted for transmitting a load via a load transmission path between the planar members. The load transmission path comprises the rotatable plates. Each of the plates comprises two flat, non-parallel contact faces, and one of the contact faces of the first rotatable plate is in permanent surface contact with one of the contact faces of the second rotatable plate. The rotatable plates are adapted for being rotated relative to each other around one of their respective normal axes.

Adjustable load transmitter

The disclosure relates to an adjustable load transmitter for adjusting an alignment between planar members separated from each other by a gap. The load transmitter comprises a set of plates to be received inside the gap, the set comprising two rotatable plates and being adapted for transmitting a load via a load transmission path between the planar members. The load transmission path comprises the rotatable plates. Each of the plates comprises two flat, non- parallel contact faces, and one of the contact faces of the first rotatable plate is in permanent surface contact with one of the contact faces of the second rotatable plate. The rotatable plates are adapted for being rotated relative to each other around one of their respective normal axes.

A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

Layout effect characterization for integrated circuits

A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Method for electrical testing of a 3-D chip stack

Growing community of inventors

Moetzingen, Germany

Martin Eckert