International Business Machines Corporation

Martin Cochet

John Francis Bulzacchelli

Troy James Beukema

Jonathan E Proesel

Timothy O Dickson

Zeynep Toprak-Deniz

Robert K Montoye

Todd Edward Takken

Bodhisatwa Sadhu

Yutaka Nakamura

Jeffrey Haskell Derby

Marcel A Kossel

Xin Zhang

Sergey Vladimirovich Rylov

Ankur Agrawal

Hyunkyu Ouh

Kevin Tien

A system and method for compensating segmented DAC intrinsic INL by adjusting the relative strength of DAC thermometer segments. In the method, the strength of each thermometer segment is adjusted sequentially to reduce INL to 0 at one point on each thermometer code range. The strength of the binary section is also adjusted to further reduce INL while conserving output amplitude. The system includes a calibration circuit that senses the DAC differential output and compares it to an ideal output generated from the same DAC via dithering between 0 and a maximum code. The compensation scheme only performs a specific type of DAC compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. The method can also be applied to calibrate a full thermometer DAC.

DAC INL compensation through thermometer segment tuning

An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

Segmented digital-to-analog converter wireline driver

A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Transmitter with uniform driver segment activity

A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m-bit multipliers and L m-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m-bit multipliers and one bit of one of the L m-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m-bit multipliers and the L m-bit multiplicands.

Integer matrix multiplication based on mixed signal circuits

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Devices, systems, and methods that can facilitate in situ probing of a discrete time circuit components are provided. According to an embodiment, a device can comprise a hold circuit that can generate a sampled signal at a holding stage. The device can further comprise an in situ probe device that can be coupled to the hold circuit that can measure one or more operating voltage values at the holding stage based on the sampled signal.

In situ probing of a discrete time analog circuit

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

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White Plains, NY, United States of America

Martin Cochet