Northern Telecom Limited

Martin C Lefebvre

Youssef A Geadah

Wayne D Grover

Carmine A Ciancibello

A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two comparators along with a simple logic circuit provide two status output signals; namely full (or not) and empty (or not ).

FIFO buffer controller

A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily 'hold' the output from the counters. This enables the counters to be re-loaded with their original 'count' to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Comparators and logic circuitry are used to provide two status output signals, namely full (or not) and empty (or not).

Message FIFO buffer controller

Asynchronous packets for a plurality of channels, each packet comprising a channel address and two information bytes, are stored in a FIFO. The address in the packet is used with a first pointer to address a RAM for storing the bytes therein. The RAM is cyclically addressed by a channel address together with a second pointer to read the bytes out synchronously to the relevant channel. Updating of the second pointer is inhibited for each channel initially to prime the RAM with bytes for the channel, and if the pointers become equal. The bytes may comprise speech samples or data. A mapped memory may be provided for converting between channel addresses in the packets and output channel addresses.

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Ottawa, Canada

Martin C Lefebvre