International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies North America Corp.

Martin Burkhardt

Jing Sha

Michael A Guillorn

Sean David Burns

Timothy A Brunner

Matthew Earl Colburn

Dongbing Shao

Allen H Gabor

Derren Neylon Dunn

Oleg Gluschenkov

Lars W Liebmann

Yongan Xu

Howard Smith Landis

Scott David Halle

Shahid Ahmad Butt

Carlos A Fonseca

Helen Wang

Gregory R McIntyre

Ronald L Gordon

Emily Elizabeth Fisch Gallagher

According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Automatic feature extraction from aerial images for test pattern sampling and pattern coverage inspection for lithography

A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Generative adversarial networks for generating physical design layout patterns of integrated multi-layers

A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Generative adversarial networks for generating physical design layout patterns

Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Classification and localization of hotspots in integrated physical design layouts

A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of patterned structures. The method also includes training, utilizing physical design layout patterns containing hotspots, a first neural network model configured to generate synthetic physical design layout patterns, and training, utilizing physical design layout patterns that do and do not contain hotspots, a second neural network model configured to classify whether physical design layout patterns contain hotspots. The method further includes generating synthetic physical design layout patterns containing hotspots by utilizing the trained first neural network model to generate synthetic physical design layout patterns and utilizing the trained second neural network model to select the synthetic physical design layout patterns containing hotspots. The method further includes evaluating manufacturability of a given patterned structure comprising at least one of the synthetic physical design layout patterns containing at least one hotspot.

Generation of hotspot-containing physical design layout patterns

Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

EUV mask for monitoring focus in EUV lithography

Method for monitoring focus in EUV lithography

This invention relates to a method of obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature. The invention also relates to an EUV mask with a special focus test target for monitoring focus in EUV lithography, and a method of fabricating this EUV mask by designing the special focus test target. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing an EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.

This invention relates to a structure for fixing phase effects on EUV mask which contains a repeating pattern with an assist feature, or a pattern with two different sized features in close proximity. The EUV mask with the repeating pattern is capable of printing a group of trenches on a photoresist layer. The invention also relates to a method of fabricating an EUV mask for fixing phase effects. The EUV mask contains an absorber layer over the multilayer reflector, and the absorber layer is patterned to form a mask pattern which contains absorptive regions and reflective regions. The absorber is in the absorptive regions, and a phase shifter is deposited at least in the whole reflective regions of the mask pattern to a thickness capable of correcting phase effects. The phase shifter has an index of refraction value is about equal to or less than that of the absorber. The thickness of the phase shifter is determined by simulation.

Structure and method for fixing phase effects on EUV mask

A pupil filter can be designed for any combination of an illumination lens and for various types of lithographic features. The pupil filter can be placed at the pupil plane of a projection optics system. For any given illumination lens providing a pupil fill within a pupil lens, a lithographic mask can be designed for the purpose of printing a one-dimensional array of line and space features or for the purpose of printing a two-dimensional array of contact holes by blocking areas, for each pixel in the pupil fill, the corresponding pixel and diffraction order pixels in the pupil lens unless +1 or &#x2212;1 diffraction order pixels fall within the area of the numerical aperture. For the purpose of frequency doubling, the pupil fill area is blocked.

Image optimization using pupil filters in projecting printing systems with fixed or restricted illumination angular distribution

Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.

Process of multiple exposures with spin castable films

A two-dimensional dense array of contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque lines. The openings in the quadrupole illumination lens are aligned along the perpendicular directions of the opaque lines. Discrete contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque subresolution assist features and discrete opaque cross patterns. Alternately, a two-dimensional array of contact holes can be printed on a negative photoresist employing a quadrupole illumination lens and a checkerboard pattern of openings. The openings in the quadrupole illumination lens are in diagonal directions.

Method to print contact holes at high resolution

A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer

A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.

Pitch-based subresolution assist feature design

A method of projecting a pattern from a mask onto a substrate comprises providing an energy source, a substrate, and a mask containing a pattern of features to be projected onto the substrate, and projecting an energy beam from the energy source though the mask toward the substrate to create a projected mask pattern image. The projected mask pattern image is created by zeroth and higher orders of the energy beam. The method then includes diffracting zeroth order beams of the projected mask pattern image to an extent that prevents the zeroth order beams from reaching the substrate, while permitting higher order beams of the projected mask pattern image to reach the substrate. Preferably, the zeroth order beams of the projected mask pattern image are diffracted at an obtuse angle.

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White Plains, NY, United States of America

Martin Burkhardt