Micron Technology Incorporated

Infineon Technologies Ag

Qimonda Ag

Siemens Aktiengesellschaft

Kabushiki Kaisha Toshiba

Martin Brox

Thomas Hein

Michael Dieter Richter

Wolfgang Anton Spirkl

Peter Mayer

Ronny Schneider

Stefan Dietrich

Natalija Jovanovic

Maksim Kuzmenka

Markus Balb

Christoph Bilger

Helmut Schneider

Andreas Schneider

Alessandro Minzoni

Mani Balakrishnan

Timothy Mowry Hollis

Roy Edgar Greeff

Karl-Peter Pfefferl

Casto Salobrena Garcia

Yasuhiro Takai

Milena Ivanov

Peter Gregorius

Robert Kaiser

Thilo Schaffroth

Naokazu Miyawaki

Mike A Killian

Elena Cabrera Bernal

Rethin Raj

Nobuyuki Umeda

Franz Freimuth

Manfred Hans Plan

Thomas Vogelsang

Christopher John Kawamura

Russell J Houghton

Dominique Savignac

Helmut Fischer

Patrick Heyne

Rex Kho

Thoai-Thai Le

Simon Muff

Joachim Schnabel

Kazimierz Szczypinski

Holger Steffens

Bernd Klehn

Sabine Kieser

Michael A Killian

Rainer Bartenschlager

Satoru Sugimoto

Eckhard Brass

Volker Kilian

Jürgen Lindolf

C Omar Benitez

Rajashekhar Rao

Sven Piatkowski

Johnathan L Gossi

Marcos Alvarez Gonzalez

Andrea Sorrentino

Jan Pottgiesser

Juan-Antonio Ocon-Garrido

Albert Graf V Keyserlingk

Oleg Sakolski

Filippo Vitale

Martin Bach

Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

Mitigating voltage overshoot at a transmission line

Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a terminated mode and an unterminated mode. A driver may be coupled with the channel, and a voltage supply for the driver may be adjusted based on the mode of the channel, such as based on whether the channel is terminated or unterminated. Adjusting the voltage supply may result in similar or otherwise desirable voltage levels on the channel for each mode of the channel.

Multi-voltage operation for driving a multi-mode channel

Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.

Temperature-dependent refresh operations

Methods, systems, and devices for memory operations that support configuring a channel, such as a command/address (C/A) channel, are described. A configuration of a C/A channel may be dynamically adapted based on power saving considerations, control information execution latency, or both. Configuring a C/A channel may include determining a quantity of pins, or a quantity of cycles, both for communicating control information over the C/A channel. The quantity of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof in some cases. The determined quantity of pins, quantity of cycles, or both may be explicitly or implicitly indicated to other devices (e.g., that use the C/A channel).

Configuring command/address channel for memory

Methods, systems, and devices for activate commands for memory preparation are described. A memory device may receive an activate command for a row of a memory bank in the memory device. The activate command may include an indicator that indicates a type of an access operation associated with the activate command. The memory device may perform, based on the type of the access operation, an operation to prepare the memory device for the access operation. The memory device may then receive an access command for the access operation after performing the operation to prepare the memory device for the access operation.

Activate commands for memory preparation

Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Channel modulation for a memory device

Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds are configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device configures a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device tracks or counts errors in the data and determine whether the threshold has been satisfied. The memory device transmits (e.g., to the host device) an indication whether the threshold has been satisfied, and the system performs functions to correct the errors and/or prevent further errors. The memory device also identifies errors in received commands or identifies errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Dynamic control of error management and signaling

Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Controlled heating of a memory device

Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.

Power-efficient access line operation for memory

Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Drive strength calibration for multi-level signaling

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Transmission failure feedback schemes for reducing crosstalk

Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output is transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Bit and signal level mapping

Methods, systems, and devices for tracking a reference voltage (also referred to as V) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

Tracking a reference voltage after boot-up

Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and signaling a second (e.g. subsequent) logic value over the channel. Adapting the current may include increasing or decreasing the current on the channel during the transition period. The degree of adaptation may be based on a difference between the first logic value and the subsequent logic value. In some cases, a logic circuit may be configured to determine a difference between the first and subsequent logic value. The logic circuit may be further configured to communicate the difference to an adaptive driver. And the adaptive driver may adapt a current of the channel based on the communicated difference.

Adapting channel current

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Offset cancellation

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Munich, Germany

Martin Brox