Metalink Corp.

Other

Martin B Pawloski

Shekhar Y Borkar

An in-circuit emulation system consisting of an emulation base and a slightly modified, flash-based COP8 architecture microcontroller. In addition to the flash memory where the User's program resides, the COP8 device includes a small ROM area with a monitor program that is used to communicate commands and data with the emulation base. Two new instructions are added, one for entering the ROM area and one for exiting it. A small set of the COP8 device's digital pins are modified to allow data, status and control to be exchanged between the COP8's CPU and the emulation base. These modified COP8 pins are recreated by the emulation base so that emulation occurs with the COP8's full complement of I/O. The content of the signals shared between the COP8 and the emulation base allows for a full range of emulation capabilities. The COP8 device is emulated in situ on the printed circuit board providing accurate operation of precision peripherals and environmental variables. The signals shared with the emulation base are routed to a standard, simple connector. The connector is configured so that the printed circuit board can be easily switched between a development system and a production system.

In-circuit emulation of single chip microcontrollers

A microcomputer system providing high performance access to external Special Function Registers (SFRs), has an 8051 architecture microcontroller modified such that the instruction stream can be externally examined and decoded by an external expansion decoder. The instruction stream can be examined and decoded regardless of whether the microcontroller fetches instructions from an internal program memory or an external program memory. Every State 6, Phase 2, data on the internal bus of the modified microcontroller is transferred to the PORT2 pins and is available to the external expansion decoder. During reset the microcontroller latches the state of the EA pin to internally determine whether to operate in ROM or ROMless mode. Thereafter, EA operates as a bi-directional control pin that, as an output, signals whether the current bus cycle is an instruction fetch, and, as an input, signals whether the microcontroller shall read the data present on a certain set of I/O pins in order to complete an SFR read operation. The expansion decoder determines whether the current instruction is one which may operate on an SFR, and if so it further decodes the SFR address associated with the current instruction, and produces appropriate read and write control signals for accessing an external SFR. The expansion decoder may contain either a fixed or programmable table of valid external SFR addresses. External SFR addresses represent peripheral functions, increased data memory or both. The system reduces the number of cycles required to access an external device in an 8051 architecture system by providing access to external devices as if they were architecturally internal devices.

System and method for producing input/output expansion for single chip

An in-circuit emulator, alternatively referred to as a microcontroller debugging system, has a control processor having I/O ports and a multiplexed address/data bus port, an emulation processor having I/O ports and a multiplexed address/data bus port, an emulation memory having address inputs, a data bus interface and a plurality of two-to-one multiplexers. The in-circuit emulator is configured such that the control processor and the emulation processor each have at least one port directly coupled to the data bus of the emulation memory without the use of external tri-state buffers, this is referred to as the shared bus. An address latch, shared by both processors, has its inputs coupled to the shared bus. The outputs of the address latch form a portion of the emulation memory address input, and are coupled to a corresponding portion of the emulation memory address inputs. The emulation processor is supplied with a clock which is selected from the group consisting of: the same clock input signal used by the control processor, a clock synchronized with the internal clock of the control processor and a clock which is asynchronous with respect to the internal clock of the control processor.

Shared bus in-circuit emulator system and method

An 8051-based microcontroller system includes an 8051 microcontroller chip which is capable of directly addressing only 64k addresses, and which is capable of addressing two kilobyte pages using a three bit embedded address portion of instruction op codes, and also includes a program memory having substantially more than 64k locations and a program memory expander including circuitry for transferring the three bits of the embedded address into an extended address register in response to detection of an AJMP or ACALL instruction from the program memory and forcing predetermined states on a multiplexed address/data bus to prevent the 8051 microcontroller chip from recognizing the AJMP or ACALL instruction. The program memory expander also includes circuitry for incrementing or decrementing the contents of the extended address register in coordination with incrementing or decrementing of an extended address including a portion in a program counter of the 8051 microcontroller chip and a portion in the extended address register, and circuitry for applying the extended address register to address inputs of the program memory.

Program memory expander for 8051-based microcontrolled system

An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 'Port 0' and 'Port 2' registers are output and functionally 'recreated'. An internal emulation mode is generated in the 8031 wherein internal SFR latch contents are output to the port leads during one state and the port drivers are tri-stated to allow in-level reading of the levels of the port leads during another state. The emulator circuit generates a 'Force Ports' pulse that causes the 'recreated' port registers of the external circuitry to 'force' external 'logic' levels onto the 8031' Port 0 and Port 2 leads.

Circuitry for producing emulation mode in single chip microcomputer

An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 'Port 0' and 'Port 2' registers are output and functionally 'recreated'. The external access (EA) lead is toggled to make the 8031 function as an 8051 during the states in which the 8051 samples its logic levels and destroys port 0 latches if configured as an 8031. Toggling the EA lead to a high level causes outputting the contents of the Port 0 and Port 2 latches to their respective leads. The emulator circuit generates a 'Force Ports' pulse that causes the 'recreated' port registers or the external circuitry to 'force' external logic levels onto the 8031 Port 0 and Port 2 leads. The address latch enable (ALE) signal is delayed until after the Force Ports signal lapses to allow the internal Port 0 logic to generate address outputs on its leads as part of the external address bus.

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Scottsdale, AZ, United States of America

Martin B Pawloski