Pact Xpp Technologies Ag

Other

Hyperion Core, Inc.

Pact Gmbh

Pact Xpp Schweiz Ag

Scientia Sol Mentis Ag

Ubitium Gmbh

Pact Informationstechnologie Gmbh

Pactgmbh

Krass, Maren

Richter, Thomas

Martin Andreas Vorbach

Frank May

Armin Nückel

Volker Baumgarte

Robert M Münch

Robert M&uuml;nch

Gerd Ehlers

Markus Weinhardt

Robert Markus Munch

Frank Lier

Prashant Rao

Jens Oertel

Dirk Reichardt

Jürgen Becker

Alexander Thomas

Joao Manuel Paiva Cardoso

Daniel Bretz

May Frank

Robert Münch

Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

High performance processor with improved microprogram execution triggered with a single issued execution trigger instruction

The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

Advanced processor architecture

High performance processor

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Providing code sections for matrix of arithmetic logic units in a processor

A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Issuing instructions to multiple execution units

A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.

Processor having a programmable function unit

An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Integrated data processing core and array data processor and method for processing algorithms

An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.

Method for providing subapplications to an array of ALUs

A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.

Methods and devices for treating and processing data

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Optimization of loops and data flow sections in multi-core processor environment

A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Multi-processor with selectively interconnected memory units

A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.

Method of transferring data between external devices and an array processor

A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.

Growing community of inventors

Karlsruhe, Germany

Martin Andreas Vorbach