Telefonaktiebolaget Lm Ericsson (publ)

Martin Anderson

Lars Sundström

Henrik Sjöland

Henrik Fredriksson

Sven Erik Mattisson

Fenghao Mu

Staffan Ek

Jim Svensson

Mattias Palm

Pietro Andreani

A digital-to-analog conversion circuit () for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, () wherein the first DAC () is of a capacitive voltage division type having a capacitive load (). Furthermore, it comprises a second DAC () having a resistive load (). An output () of the first DAC () and an output () of the second DAC () are connected, such that said capacitive load () and said resistive load () are connected in parallel.

Digital-to-analog conversion circuit

A DAC () is disclosed. It comprises an input port comprising N input terminals p, p, . . . , pconfigured to receive voltages representing N input bits b, b, . . . , b, respectively, wherein the significance of bis higher than for bfor j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit () comprising N capacitors C, C, . . . , Cwith capacitance C, each having a first terminal and a second terminal. Capacitor Cis connected with its first terminal to the terminal pof the input port. For each j=1, 2, . . . , N&#x2212;1, the capacitor ladder circuit () comprises a capacitor () with capacitance xC connected between the second terminal of capacitor Cand the second terminal of capacitor C. The DAC () also comprises an input circuit () connected to the input port comprising at least one capacitor (-), each connected between a unique one of the input terminals p, p, . . . , pof the input port and signal ground.

Digital-to-analog converter

A TI ADC circuit () comprises a plurality of L analog inputs (---) and a plurality of L digital outputs (---). The i:th analog input (-) is for receiving an i:th analog input signal. The i:th digital output (-) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit () comprises a set () of sub ADCs (-&#x2014;-K). The TI ADC circuit () is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (-&#x2014;-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer &#x3e;1. The number K of sub ADCs in the set () of sub ADCs (-&#x2014;-K) exceeds L&#xb7;M. TI ADC circuit () comprises a control circuit () configured to select, for each input sample of each of the L analog input signals, which available sub ADC (-&#x2014;-K) in the set () of sub ADCs that should operate on that input sample, such that at least some of the sub ADCs (-&#x2014;-K), over time, operate on input samples of each of the L analog input signals.

TI ADC circuit

A circuit for calibration measurements comprises a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller having a clock signal input and connected to the output of the comparator circuit. The controller is arranged to control the discharge switch to discharge the capacitor, change state of the switch to enable charging of the capacitor and count clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor, wherein the controller is arranged to determine a calibration measurement from counted number of clock signal pulses. A method, computer program and electronic device are also disclosed.

Circuit for calibration measurements, method, computer program, and electronic device

A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter () to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (); a digital-to-analog converter () to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators () in series, each having a feedback path comprising the analog-to-digital converter () in cascade with a digital-to-analog converter (), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.

Frequency selective circuit configured to convert an analog input signal to a digital output signal

A continuous-time &#x394;&#x3a3;-ADC () is disclosed. It comprises a sampled quantizer () arranged to generate samples y(n) of a digital output signal of the &#x394;&#x3a3;-ADC () at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (). Furthermore, the &#x394;&#x3a3;-ADC () comprises one or more DACs (-), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (). Moreover, the &#x394;&#x3a3;-ADC () comprises a continuous-time analog network () arranged to generate the analog input signal to the quantizer () based on the feedback signal(s) from the one or more DACs (-) and an analog input signal to the &#x394;&#x3a3;-ADC (). At least one DAC () of the one or more DACs () comprises two switched-capacitor DACs () arranged to operate on the same input but with a mutual delay in time. A corresponding radio receiver circuit (), a corresponding intergrated circuit (), and a corresponding radio communication apparatus () are also disclosed.

Analog-to-digital converter

A mixer unit () for frequency translating, based on an LO signal, an input signal having one or more input signal components is disclosed. The mixer unit has a signal processing path (--) from each Input terminal (&#x2212;) to each output terminal (_I+,_I&#x2212;,_Q+,_Q&#x2212;) of the mixer unit (), The LO signal has an associated LO signal component (LO_Ia-d, LO_Qa-d) for each signal processing path. The mixer unit () comprises a plurality of mixer switches (-N) and a control unit (). The control unit () is adapted to, for each signal processing path (--), dynamically select an associated subset, in the following denoted active switch subset, of the plurality of mixer switches (-N) for operation in the signal processing path (-) such that which of the plurality of mixer switches (-N) belong to said active switch subset varies in time. At any instant in time, the union of all the active switch subsets is a strict subset, denoted combined active subset, of the plurality of mixer switches (-N). The control unit () is further adapted to activate only the mixer switches (-N) in said combined active subset by, for each mixer switch (-N) in the combined active subset, supplying the corresponding LO signal component to the mixer switch. A related radio receiver circuit (), a related radio communication apparatus (), and a related method are also disclosed.

Mixer unit

A continuous-time &#x394;&#x3a3;-ADC () is disclosed, comprising a sampled quantizer () arranged to generate samples y(n) of a digital output signal of the &#x394;&#x3a3;-ADC () at sample instants nT. The &#x394;&#x3a3;-ADC () further comprises two or more DACs (-), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (), and a continuous-time analog network () arranged to generate an analog input signal to the quantizer () based on the feedback signal(s) from the two or more DACs (-) and an analog input signal to the &#x394;&#x3a3;-ADC (). At least a first DAC () of the two or more DACs (-) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a1)T and (&#x3b7;+&#x3b2;1)T, wherein 0&#x3c;&#x3b1;1&#x3c;&#x3b2;1&#x3c;1. A&#xed; least a second DAC () of the two or more DACs (-) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a2)T and (&#x3b7;+&#x3b2;2)T, wherein 0&#x3c;a2&#x3c;1&#x3c;&#x3b2;2. The first DAC () is located in a first feedback loop and the second DAC () is located in a second feedback loop, which is an outer feedback loop relative to the first feedback loop. A corresponding radio receiver circuit, a corresponding integrated circuit, and a corresponding radio communication apparatus are also disclosed.

In one aspect, the present invention exploits the termination conductances of a time-discrete harmonic mixer as another degree of freedom in configuring the mixer to meet given harmonic rejection performance requirements while using reduced number of unit cells. The values of these termination conductances are purposefully configured to introduce a desired non-linearity in quantization of the mixer transconductance by the unit cells. The non-uniform quantization produces a non-linear fitting of the transconductance levels to the transconductance points defining the target sinusoidal waveform. As a consequence of its termination conductance configuration, the contemplated mixer achieves levels of harmonic rejection with that would not be met if the reduced number of unit cells operated with uniform quantization. As a further advantage, the manipulated conductance values generally are lower than those used in conventional designs, e.g., on par with the maximum conductance of the mixer, as provided by mixer's set of unit cells.

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Löddeköpinge, Sweden

Martin Anderson