Coherent Logix, Inc.

Nline Corporation

Martin A Hunt

Michael B Doerr

Michael W Bruns

Jan D Garmany

Manjunath H Siddaiah

Michael B Solka

John C Sievers

Stephen V Wood

X Long Dai

Daemon G Anastas

Carl S Dobbs

Tommy Kinming Eng

Bichuan Shen

Daemon G Arastas

System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.

DNA alignment using a hierarchical inverted index table

Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.

Low latency video codec and transmission with parallel processing

Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.

Surround view generation

A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficiently and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.

Distributed architecture for encoding and delivering video content

Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.

System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.

Three dimensional display system

Three dimensional display compute system

A system and method are described for an image registration system and method including a registration engine that receives complex image data for corresponding images. The registration engine generates a correlation map between the complex image pair for relative translation by calculating an inverse of the complex conjugate product of the frequency data of the first image and the frequency domain data of the second, corresponding, image. The frequency domain data may be obtained using Fast Fourier transform-based techniques.

System and method for registering complex images

In the present disclosure a system and method are described for removing fixed pattern noise. The system includes a positioning system for holding and positioning a target, an optical system for capturing images or the target, and a fixed pattern noise removal engine for identifying and removing fixed pattern noise. The fixed pattern noise removal engine preferably identifies fixed pattern noise by analyzing a reference image and target image.

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Austin, TX, United States of America

Martin A Hunt