Nxp B.v.

Vector Fabrics B.v.

Martijn Rutten

Josephus Theodorus Johannes Van Eijndhoven

Paul Stravers

Evert-Jan Daniël Pol

Jos Van Eijndhoven

Maurice Kastelijn

Pieter Van Der Wolf

Om Prakash Gangwal

Evert J Pol

Alexey Rodriguez

Wouter Swierstra

Tommy Kamps

A method of generating an embedded system () from an original computer program () which embedded system () provides a parallellized hardware () and software () implementation of the original computer program (), which parallellized implementation () satisfies one or more criteria regarding hardware constraints of the embedded system (). The system provides partitioning of functionality from the original computer program () using structural and behavioral program models and detects streaming and memory dependencies to improve the partitioning, relying on added indications of source lines and variables in said original computer program to relate partitions and dependencies in the program model with locations in the original program source code.

Embedded system performance

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.

Embedded system development

Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Data processing system having multiple processors and a communications means in a data processing system

The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor () for processing streaming data, at least one cache memory () having a plurality of cache blocks (), wherein one of said cache memories () is associated to each of said processors (), and at least one cache controller () for prefetching data into said cache memory (), wherein one of said cache controllers () is associated to each of said cache memories (). Said cache controller () comprises determining means () for identifying at least one location in said cache memory () containing first data, which is predicted to be dismissible without penalty and prefetch means () for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.

Data processing system with prefetching means

A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit () and a computational unit. The administration unit of a writing processor maintains information defining a section in the memory which is free for storing data objects for readout by the reading processor. The administration unit of the reading processor maintains information defining a section in the memory in which the writing processor has written completed data for the data objects. The processors are arranged to signal a message to another processor via a processor synchronization channel for updating the information in the administration unit of said other processor.

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Eindhoven, Netherlands

Martijn Rutten