Bull S.a.

Marta Zorrilla

Philippe Chantraine

Vivian Blanchard

The invention relates to an automated method for inserting dummy surfaces () into the various layers of the physical design () of multilayer integrated circuits organized in interconnected units () containing interconnected blocks () composed of interconnected cells (), implemented by an integrated circuit design system (). The multilayer integrated circuit design (), stored in the design system () is implemented layer by layer, through selective insertion of patterns of dummy surfaces (), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design () of the integrated circuits, by means of individual implementation of the interconnected blocks () and first interconnection routing () for said interconnected blocks () and individual implementation of the interconnected units () and second interconnection routing () for said interconnected units (). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks () of the integrated circuit.

Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit

An automated method for inserting dummy surfaces into the various layers of the physical design of a multilayer integrated circuit is implemented by an integrated circuit design system. The integrated circuit is organized in interconnected units containing interconnected blocks composed of interconnected cells. The multilayer integrated circuit design, stored in the design system is implemented layer by layer, through selective insertion of patterns of dummy surfaces. The selective insertion is based on an insertion hierarchy with respect to the hierarchy of the physical design of the integrated circuit, by means of individual implementation of the interconnected blocks and first interconnection routing for said interconnected blocks and individual implementation of the interconnected units and second interconnection routing for said interconnected units. The patterns of dummy surfaces are established selectively in accordance with the methods used for designing the blocks of the integrated circuit. The methods used for designing the interconnected blocks include a standard cell method and a custom cell method.

Via studs (23) of the multi-layer structure (12) are formed on a uniform metal layer that is subsequently etched to form the conductors (17) of a conductive layer of the multi-layer structure.

Method for forming the multi-layer structure of a connection board of at

A method for deposition of an insulating layer on a conductive layer of the multi layer structure of a connection board of a VLSI circuit and a connection board formed by the method. The formation of an insulating layer coplanar with the upper surface of the vias (21) of the conductive layer (16a, 16b) is done by etching of an insulating layer (26) formed of a plurality of successive strata (22, 23, 24, 25) until a surface is obtained that has steps of a maximum height (S4) substantially equal to or less than a desired valve (V) corresponding to the desired degree of planarity of the final insulating layer.

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Fontenay le Fleury, France

Marta Zorrilla