John Fluke Mfg. Co., Inc.

Marshall H Scott

John D Polstra

Alden J Carlson

Kasi S Bhaskar

Bruce T White

Dennis L Lambert

Anthony R Vannelli

Robert E Cuckler

Alastair N Couper

W Douglas Hazelton

An improved testing apparatus and method for testing the kernel of a microprocessor based unit under test (UUT) in which connection to the UUT is made at both the memory connection socket and at the microprocessor with the microprocessor being in place and active in the UUT. The apparatus and method permits substantially full diagnostics of the kernel to be carried out in a systematic and automated manner in which the requirement of manual probing of the UUT is minimized. Connections at the microprocessor permit the development of high resolution sync signals for verification and evaluation of test results. The testing protocol implemented in the method includes the use of testing primitives which permit the development of a signature for each address and data bus line for the identification of the type as well as the location of any faults discovered by the apparatus. The method of testing exploits bootstrapping techniques including three primitives for bus test, data stimulus and address stimulus to optimize simultaneous testing and circuit fault diagnosis.

Kernel testing interface and method for automating diagnostics of

A method and system for testing and troubleshooting microprocessor-based electronic systems employs memory emulation techniques as well as other techniques to provide complete functionality tests and fault location. Fine-resolution sync pulses may be generated at preselected time positions during a bus cycle of interest to facilitate full troubleshooting fault isolation. Other features include bus testing using memory emulation techniques, using the chip select line of ROMs to encode test results, and techniques that keep a target microprocessor functioning in a system in which the kernel is dead.

Memory emulation method and system for testing and troubleshooting

Circuit faults in an electronic system are isolated by a programmed computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the UUT. The measured response is compared to a predetermined response corresponding to an operational UUT to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the UUT. The computer is further programmed to have a form of 'intuition' whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of UUT.

Computer assisted fault isolation in circuit board testing

A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

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Woodinville, WA, United States of America

Marshall H Scott