International Business Machines Corporation

Maroun Kassab

Leah M Pastel

Rao H Desineni

Franco Motika

Leendert M Huisman

Leah Marie Pfeifer Pastel

William Vincent Huott

Leah M Pfeifer Pastel

Adam E Trojanowski

James William Adkisson

John Maxwell Cohn

Mary Prilotski Kusko

Leah M P Pastel

Mohammed Fazil Fayaz

David E Sweenor

Julie L Lee

Embodiments of the disclosure include a method for data mining shape based data, the method includes receiving shape data for each of a plurality of data entries and creating a first abstract from the shape data for each of the plurality of data entries. The method also includes organizing the first abstracts into a plurality of groups based on a criterion and creating a second abstract for each data entry in the plurality of groups based on the criterion and information derived from the first abstract.

Data mining shape based data

Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Identifying defects

A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

Insertion of faults in logic model used in simulation

A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.

Method for testing integrated circuits

A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.

Method for determining features associated with fails of integrated circuits

Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

System and method for signature-based systematic condition detection and analysis

Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

Methods and apparatus for testing a scan chain to isolate defects

An iterative process for identifying systematics in data is provided. In general, a set of data is processed based on a signature definition to create a set of signature data. The set of signature data is then analyzed to identify common signatures. The set of signature data is modified, using knowledge of the common signature(s), creating a revised set of signature data. The revised set of signature data is then analyzed again to identify new common signatures, if any. The modifying and analyzing steps are repeated until no new common signatures are identified. When no new common signatures are identified, the identified common signatures are reported.

Iterative process for identifying systematics in data

A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.

Learning based logic diagnosis

Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

Growing community of inventors

St-Eustache, Canada

Maroun Kassab