U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Nxp B.v.

Pace Micro Technology Plc

U.S. Phillps Corporation

Marnix Claudius Vlot

Paul E R Lippens

Richard Cees Spiero

Terence A Douglas

Vincent Pierre Martinez

Alessio Filippi

Roger Cuppens

Frederik Zandveld

Cornelis Marinus Moerman

Rudolf H Bloks

Rogatus H Wester

Graham G Thomason

Joost-Pieter Katoen

Paulus A Van Niekerk

In connection with an RF communication system, exemplary aspects involve a method for use in a communication system in which a first system (e.g., 802.11) that is asynchronously based and which is susceptible to interference from a second system (e.g., synchronous-based LTE-CV2X). Such interference is due to the frequency spectrum used by the first and second systems overlapping. To mitigate interference issues, example methods spreads out the times for messages in the first system, based on information concerning occupancy of the channel, and transmitting them relative to the end of a cycled transmission allocated for use by the second system.

Mitigating interference in channel access involving multiple systems

The invention relates to a transmission system () comprising a transmitter () and a receiver (). The transmitter () is arranged for transmitting a plurality of signals (), e.g. radio and/or television signals. The plurality of signals () comprise mutually corresponding signals, e.g. analog and digital signals of the same channel or program. Alternatively, the mutually corresponding signals may comprise standard definition and high definition signals of the same channel or program. The receiver () is arranged for receiving at least part of said plurality of signals (). The transmitter () is arranged for transmitting information () identifying said mutually corresponding signals and the receiver () is arranged for receiving said information (). The receiver () comprises a selector () for selecting on basis of said information () at least one () of the mutually corresponding signals. In the way, the receiver () can automatically select the most appropriate signal (), e.g. for inclusion in a list of available channels/programs or for reproduction.

Transmission system

The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Stack oriented data processing device

The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to, top of stack including a push or pop.

The data processing circuit contains a non-volatile memory. Error correction is provided for computing individual correction data for correcting an error in an individual data unit in the non-volatile memory. The individual correction data is computed from a combination of a plurality of data units read from the non-volatile memory. A correction data store stores the individual correction data. Memory access is signaled to the correction data store, which outputs data corrected according to the correction data when said individual data unit is read. The circuit comprises error correction trigger means for triggering the error correction computing means to perform said computing independent of reading of the individual data from the non-volatile memory.

Data processing circuit with non-volatile memory and error correction circuitry

Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Processor architecture with independently addressable memory banks for storing instructions to be executed

In an instruction a relative jump distance is expressed as a number of instructions rather than as a number of addresses. Instructions have various lengths. After encountering the instruction the processing device loads the following instructions but suppresses execution of a set of instructions that consists of the number of instructions expressed in the relative jump instruction.

Data processing device with relative jump instruction

A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.

Data processing system with reduced look-up table for a function with

An audio system has an attacher station for attaching to and decoding an audio representation channel, which also has a first auxiliary information sub-channel. A user station is fed by the attacher station through a unidirectional interface and receives the auxiliary information in an application context under control of a user interface for selective displaying. The attacher station extracts the auxiliary information from the channel. The system also has a framework data generator that is instantiatable by information from the information sub-channel, and a framework packetizer fed by the generator for supplementing the audio representation channel on said unidirectional interface in a second auxiliary information sub-channel by packetized and instantiated application information for the user station.

Audio data system with a first information sub-channel, extraction means

A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output. The system includes a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus including a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit. The destination apparatus including a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.

Signal processing system

A communication system has multiple and uniformly weighted station interconnected by a shared digital bus. A particular station comprises globally relevant information, and, with a predetermined maximum recurrence time, transmits a data packet representing such item to any other interested station. If unanimous counter signalization occurs, the item is in order, other wise updating thereof is undertaken. The unanimity is either by positive signalization, or by default.

Multi-station bus system having means for polling and updating of

The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connectors each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switching means each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switching means (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switching means (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.10) are adapted to couple the second (b) or the third (c) terminal to the first terminal (a) under the influence of a first or second control signal respectively, supplied by the control signal generator (5.11). The control signal generator (5.11) has a first terminal (10) coupled to the control signal terminals (5.3, 5.6) of the first and second connectors, and an output terminal (12, 13) for supplying the first and second control signal for the first and second switches (5.9, 5.10) respectively. The signal input terminal (5.7) of the third connector is coupled to the third terminals (c) of the first and second switches (5.9, 5.10). The control signal generator (5.11) is further adapted to generate a control signal for at least one of the first and the second switches, in response to the control signal applied to a second terminal (11). Further an input-output circuit is provided for coupling a controller included in the control signal generator (5.11) to line 10 of the SCART cable.

Apparatus for use in an interconnection system

The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connector each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switches each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switches (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switches (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.10) are adapted to couple the second (b) or the third (c) terminal to the first terminal (a) under the influence of a first or second control signal respectively, supplied by the control signal generator (5.11). The control signal generator (5.11) has a first terminal (10) coupled to the control signal terminals (5.3, 5.6) of the first and second connectors, and an output terminal (12, 13) for supplying the first and second control signal for the first and second switches (5.9, 5.10) respectively. The signal input terminal (5.7) of the third connector is coupled to the third terminals (c) of the first and second switches (5.9, 5.10). The control signal generator (5.11) is further adapted to generate a control signal for at least one of the first and the second switches, in response to the control signal applied to a second terminal (11). Further an input-output circuit is provided for coupling a controller included in the control signal generator (5.11) to line 10 of the SCART cable.

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Eindhoven, Netherlands

Marnix Claudius Vlot