Bitmicro Networks, Inc.

Bitmicro LLC

Marlon Basa Verdan

Ricardo H Bruce

Cyrill Coronel Ponce

Elsbeth Lauren Tagayo Villapana

Jarmie De La Cruz Espuerta

Avnher Villar Santos

Rey H Bruce

Elsbeth Lauren Tagayo-Villapaña

Jarmie Dela Cruz Espuerta

Rowenah Michelle Jago-on

Margaret Anne N Somera

Rowenah Michelle D Jago-on

Maria Eliza B De Belen

Ron Kelvin B Palacol

Arnaldo Cristobal

In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. In another embodiment of the invention, a method comprises: providing a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. Data can be stored into the serial chain, wherein the data is written by a memory transaction from a host.

Multi-dimensional computer storage system

In an embodiment of the invention, an apparatus comprises: a first flash module comprising a first flash device; and a second flash module comprising a second flash device; wherein the first flash module and second flash module are coupled by a flash interconnect; wherein the first flash device is configured to store a first data stripe of a data and wherein the second flash device is configured to store a second data stripe of the data. In another embodiment of the invention, a method comprises: storing, in a first flash device in a first flash module, a first data stripe of a data; and storing, in a second flash device in a second flash module, a second data stripe of the data; wherein the first flash module and second flash module are coupled by a flash interconnect. In yet another embodiment of the invention, an article of manufacture comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: storing, in a first flash device in a first flash module, a first data stripe of a data; and storing, in a second flash device in a second flash module, a second data stripe of the data; wherein the first flash module and second flash module are coupled by a flash interconnect.

Scatter-gather approach for parallel data transfer in a mass storage system

In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

Data storage system with configurable prefetch buffers

In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

Bus arbitration with routing and failover mechanism

In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.

Interrupt coalescing

An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.

In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation

A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.

Network of memory systems

The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or both which are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the disadvantages of the prior art.

Growing community of inventors

Paranaque, Philippines

Marlon Basa Verdan