Arm Limited

International Business Machines Corporation

Other

Marlin Wayne Frederick, Jr

Karen Lee Delk

Yew Keong Chong

Andy Wangkun Chen

Gus Wai-Yan Yeung

Sriram Thyagarajan

Bruce Joseph Ronchetti

Ronald Paxton Preston

Tom Shore

Brian Tracy Cline

Larry Edward Thatcher

Xiaoqing Xu

Martin Jay Kinkade

James Dennis Dodrill

Jean-Luc Pelloie

Paul Christopher De Dood

Daniel J Albers

David Paul Clark

Sharath Koodali Edathil

Jerry Chaoyuan Wang

Stephen Andrew Kvinta

Chih-Wei Huang

David William Granda

Ravindra Narayana Rao

Lena Ahlen

Peter Juergen Klim

Christopher McCall Durham

James Edward Myers

David Walter Flynn

David James Shippy

Robert Campbell Aitken

Donald George Mikan, Jr

Gregory Munson Yeric

Eric Bernard Schorn

Ettore Amirante

Cang Ngoc Tran

Akhtar Waseem Alam

James Edward Dunning

Valentina Gomez

Sumana Pal

Sanjay Bhagwan Patil

Thanusree Achuthan

Ashwani Kumar Srivastava

James David Shiffer, Iii

Yanbin Jiang

Kerry Karl Nick

Stefan Charles Creaser

Sharrone Rena Smith

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

Sylvia Xiuhui Li

An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

Power distribution

Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

Cell architecture with backside power rails

Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.

Power distribution circuitry

Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

Computer implemented system and method for generating a layout of a cell defining a circuit component

Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.

Power rail stitching technique

Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.

Metal layout techniques

Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

Memory structure with bitline strapping

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

Power grid healing techniques

Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.

Sleep signal stitching technique

An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

Via placement within an integrated circuit

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.

Integration fill technique

Growing community of inventors

Austin, TX, United States of America

Marlin Wayne Frederick, Jr