Imec

Imec Vzw

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Marleen Van Hove

Brice De Jaeger

Serge Vanhaelemeersch

Joff Derluyn

Stefaan Decoutere

Steve Stoffels

Pawel Malinowski

Herbert Struyf

Werner Boullart

Jan Van Olmen

Vasyl Motsnyi

Celso Cavaco

Puneet Srivastava

Dirk Hendrickx

A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350&#xb0; C. to 500&#xb0; C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Method for fabricating CMOS compatible contact layers in semiconductor devices

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

Low temperature ohmic contacts for III-N power devices

A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450&#xb0; C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.

CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof

A III-nitride device is provided comprising a semiconductor substrate; a stack of active layers on the substrate, each layer comprising a III-nitride material; a gate, a source and a drain contact on the stack, wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and a trench in the substrate extending from a backside of the substrate (side opposite to the one in contact with the stack of active layers) to an underlayer of the stack of active layers in contact with the substrate, the trench completely surrounding the drain region, being positioned in between an edge of the gate region towards the drain and an edge of the drain region towards the gate and having a width such that the drain region of the substrate is substantially made of the semiconductor material.

Method for fabrication of III-nitride device and the III-nitride device thereof

A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 &#x3bc;m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Damascene contacts on III-V CMOS devices

A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Dual damascene patterning method

Growing community of inventors

Blanden, Belgium

Marleen Van Hove