Hyperion Core, Inc.

Pact Xpp Technologies Ag

Other

Pact Xpp Schweiz Ag

Scientia Sol Mentis Ag

Krass, Maren

Richter, Thomas

Markus Weinhardt

Martin Andreas Vorbach

Frank May

Volker Baumgarte

Armin Nückel

Jürgen Becker

Joao Manuel Paiva Cardoso

A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Issuing instructions to multiple execution units

An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Integrated data processing core and array data processor and method for processing algorithms

A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.

Method for processing data

A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Data processing system having integrated pipelined array data processor

The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Data processing method and device

A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Growing community of inventors

Munich, Germany

Markus Weinhardt