Intel Corporation

Markus T Metzger

Beeman C Strong

Robert Wiesner

Ravi L Sahita

Michael Lemay

Yuriy Bulygin

Thilo Schmitt

Oender Karpat

Khem Raj

An embodiment of an integrated circuit may comprise a processor and circuitry coupled to the processor to generate non-timing packets associated with a trace of an execution of code on the processor, generate timing packets associated with the trace of the execution of the code on the processor, wherein the timing packets include at least a full timestamp timing packet and a periodic timing packet, identify a low density section of the trace of the execution of the code on the processor, and suppress generation of periodic timing packets during the identified low density section of the trace of the execution of the code on the processor. Other embodiments are disclosed and claimed.

Processor trace with suppression of periodic timing packets for low density trace sections

Technologies for bridging trace gaps include a computing device that traces execution of a program to generate an execution trace and identifies a trace gap in the execution trace. The computing device generates a first call stack that corresponds to a location immediately before the trace gap and a second call stack that corresponds to a location immediately after the trace gap. Each call stack identifies a list of functions, and each function corresponds to a source function of the program. The computing device evaluates connection pairs between the first call stack and the second call stack to determine whether each connection pair is valid and, for each valid connection pair, a number of matching functions. The computing device selects a connection pair that is valid and has a largest number of matching functions and bridges the trace gap with the selected connection pair. Other embodiments are described and claimed.

Technologies for bridging gaps in execution traces

Technologies for control flow exploit mitigation include a computing device having a processor with real-time instruction tracing support. During execution of a process, the processor generates trace data indicative of control flow of the process. The computing device analyzes the trace data to identify suspected control flow exploits. The computing device may use heuristic algorithms to identify return-oriented programming exploits. The computing device may maintain a shadow stack based on the trace data. The computing device may identify indirect branches to unauthorized addresses based on the trace data to identify jump-oriented programming exploits. The computing device may check the trace data whenever the process is preempted. The processor may detect mispredicted return instructions in real time and invoke a software handler in the process space of the process to verify and maintain the shadow stack. Other embodiments are described and claimed.

Technologies for control flow exploit mitigation using processor trace

A method according to one embodiment includes the operations of receiving a list of one or more data race analysis targets, wherein the data race analysis targets comprise at least one of a source file name, source file line, function name, variable name or target address range; generating a data race analysis filter, wherein the data race analysis filter comprises a data structure including memory address ranges based on the list of data race analysis targets; and performing a data race analysis on a memory access, wherein the memory access is associated with memory addresses included in the data race analysis filter.

Data race analysis with improved detection filtering

Embodiments of a method and system for compiling code, such as program-generated code, are disclosed herein. The method and system efficiently encode combined range and stride checks. For example, the method and system are operable to encode combined range and stride checks as they occur in a translation of switch statements. The method and system can generate code to perform the range and stride check, and to branch to the case body, if the range and stride checks are successful. The various embodiments may operate to provide an efficient code transformation, better code density, and processing performance. Other embodiments are described and claimed.

Method and system for efficient range and stride checking

A system for performing code optimization is described which includes an optimizing analyzer within a compiler to generate a first optimizing transformation and a second optimizing transformation and their satisfying conditions for a compiled code. An optimization transformation module is placed within a linker to determine which of the first and second optimizing transformations should be selected when the compiled code is linked with other compiled codes, and to execute the selected one of the first and second optimizing transformations at link-time. A method of performing code optimization is also described.

Method and system for performing link-time code optimization without additional code analysis

The method and apparatus for compiling high level code is described. A method may be utilized that may include integrating the allocation of registers, scheduling instructions, and selecting code functions to produce an intermediate representation of a high level code segment with scheduled instructions. Additionally, a modular conflict handler may be utilized to resolve register and/or scheduler conflicts as may be required or useful in compiling the high level code. Also, a modular transformation interface may be utilized to invoke analyzers as may be required or useful to generate a compiled version of the high level code.

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Ulm, Germany

Markus T Metzger