Infineon Technologies Ag

Markus Schwerd

Martin Seck

Johann Helneder

Martina Hommel

Thomas Goebel

Andrea Mitchell

Heinrich Körner

Heinrich Koerner

Wolfgang Klein

Holger Torwesten

Michael Schrenk

Stefan Drexl

Rudolf Lachner

Armin Fischer

Alexander Von Glasow

Wolfgang Walter

Heinrich Kôrner

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Process for producing a multifunctional dielectric layer on a substrate

An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Integrated circuit with capacitor and method for the production thereof

An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

System and method for integrated circuit arrangement having a plurality of conductive structure levels

A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

Integrated connection arrangements

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Integrated circuit with improved component interconnections

To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer () and a dielectric auxiliary layer () are deposited on a first electrode (). The protective layer and the auxiliary layer () are then opened up () via the first electrode. Then, a dielectric layer () is produced, and the metal track stack () for the second electrode is then applied to the dielectric layer (). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Integrated semiconductor product comprising a metal-insulator-metal capacitor

An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.

Integrated circuit having a thermally shielded electric resistor trace

A capacitor stack in a layer structure of an integrated component has the same layer sequence as an adjacent interconnect, with the exception of a dielectric interlayer. This significantly facilitates the fabrication of vias.

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Holzkirchen, Germany

Markus Schwerd