Amkor Technology, Inc.

Olin Corporation

Markus K Liebhard

Thomas P Glenn

Steven Webster

Jeffrey Alan Miks

Paul Robert Hoffman

Donald Craig Foster

Kenneth Kaskoun

Frederic Bertholio

Vincent DiCaprio

Paul R Hoffman

Ju-Hoon Yoon

Dae-Byung Kang

In-Bae Park

A lead-frame method and assembly for interconnecting circuits within a circuit module allows a circuit module to be fabricated without a circuit board substrate. Integrated circuit dies are attached to a metal lead-frame assembly and the die interconnects are wire-bonded to interconnect points on the lead-frame assembly. An extension of the lead-frame assembly out of the circuit interconnect plane provides external electrical contacts for connection of the circuit module to a socket.

Lead-frame method and assembly for interconnecting circuits within a circuit module

An edge stiffener added to a lead-frame based circuit module provides protection of the peripheral flange of the circuit module during handling and manufacturing processes. The edge stiffener may be coupled to leads of the lead-frame for providing electrical contacts at the periphery of the circuit module or may be form widened portions of a tie bar that is connected to the lead frame by leads extending through gaps between the ends of the edge stiffener portions. Singulation of the circuit module will result in edge stiffener portions that are not coupled to the lead frame, but are secured within the encapsulant.

Lead-frame method and circuit module assembly including edge stiffener

To form an image sensor package, a window is mounted above an active area on an upper surface of an image sensor. The image sensor further includes a plurality of bond pads on the upper surface. Interior traces on a lower surface of a step up ring are aligned with the bond pads on the upper surface of the image sensor. Bumps are formed between the interior traces and the bond pads thus flip chip mounting the step up ring to the image sensor. The step up ring is mounted such that the window is located in or adjacent a central aperture of the step up ring. An underfill material is applied into the central aperture. The underfill material flows from the central aperture between the lower surface of the step up ring and the upper surface of the image sensor. The underfill material encloses the bumps. The underfill material is cured, if necessary, to form a package body. The package body enhances the reliability of the image sensor package by preventing the failure of the bumps and preventing the associated dismounting of the step up ring.

Chip size image sensor bumped package fabrication method

To form an image sensor package, a window is mounted above an active area on an upper surface of an image sensor. A noncritical region of the upper surface of the image sensor is between the active area and bond pads of the image sensor. A lower surface of a step up ring is mounted above the noncritical region of the upper surface of the image sensor. An upper surface of the step up ring includes a plurality of electrically conductive traces. Bond wires are formed between the bond pads of the image sensor and the electrically conductive traces on the upper surface of the step up ring. The step up ring is mounted so that the window is located in or adjacent a central aperture of the step up ring.

Chip size image sensor wirebond package fabrication method

A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process. Using the pre-testing results, the method eliminates wasteful packaging of defective chips. The quality and/or grade of packaged units are marked on the chips in accordance with the pre-testing data, thereby enabling defective packages to be distinguished from good packages without need for post-singulation testing. The method permits using only good circuit pattern units, thereby preventing expensive chip units from being packaged with defective pattern units. In addition, the method permits both a package pick-and-place step and a package marking step to be combined into a single operation using a single device.

Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques

An image sensor package includes an image sensor having an upper surface. The image sensor further includes an active area and bond pads on the upper surface. A window is supported above the active area by a window support. Interior traces are formed on a lower surface of a step up ring. Electrically conductive bumps are formed between the interior traces on the lower surface of the step up ring and the bond pads on the upper surface of the image sensor thus flip chip mounting the step up ring to the image sensor. Electrically conductive vias extend through the step up ring to electrically connect the interior traces to exterior traces formed on an upper surface of the step up ring.

Chip size image sensor bumped package

An image sensor package includes an image sensor having an upper surface. The image sensor further includes an active area and bond pads on the upper surface. A window is supported above the active area by a window support. A step up ring is mounted above a noncritical region of the upper surface of the image sensor between the active area and the bond pads. Electrically conductive traces on the step up ring are electrically connected to the bond pads by bond wires. An inner package body is formed between the step up ring and the window support and mechanically locks the window in place. An outer package body is formed to enclose the bond wires, the bond pads, and outer sides of the step up ring. The outer package body has outer sides coplanar with sides of the image sensor such that the image sensor assembly is chip size.

Chip size image sensor in wirebond package with step-up ring for electrical contact

An assembly and method for mounting thick integrated circuit packages within a low-profile circuit module provides a low cost alternative to special integrated circuit packaging requirements. Pre-packaged thin-small-outline-packages (TSOP), thin-plastic-quad-flatpack (TQFP) and other similar surface mount packages may be used within a low-profile circuit module, using the techniques and structures of the present invention. A straight lead package is mounted within a cavity in the circuit module substrate, so that the effective height of the integrated circuit package is reduced. Curved lead packages are used by straightening or sawing the leads before mounting.

Low profile mounting of thick integrated circuit packages within low-profile circuit modules

A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.

Semiconductor package with warpage resistant substrate

There is provided a component for an electronic package and a method for the manufacture of that component. The component has a metallic substrate with a surface coated by a dielectric. A centrally disposed cavity extends through the dielectric into the metallic substrate to a depth, D.sub.1. Circumscribing and abutting this cavity is an annular channel having a depth D.sub.2 that is less than D.sub.1. A semiconductor device bonded to the base of the cavity is electrically interconnected to both circuit traces formed on the dielectric coating and to the annular channel. A method of forming the annular channel is to mechanically mill a precursor annular channel having an outer wall a desired distance from the sidewalls of the metallic substrate and a width substantially greater than the desired width of the annular channel. A cavity is then formed in the region circumscribed by the outer wall of the precursor annular channel. The perimeter of this cavity approaches the outer wall of the precursor annular channel, terminating a desired distance from the outer wall such that that portion of the annular channel having a depth D.sub.2 is a desired width, typically less than 0.015 inch.

Growing community of inventors

Gilbert, AZ, United States of America

Markus K Liebhard