Minima Processor Oy

Markus Hiienkari

Lauri Koskinen

Matthew Turnquist

Jani Mäkipää

Jani MÄKIPÄÄ

A control system for controlling an operating voltage of an electronic device is presented. The electronic device includes a timing event detector responsive to timing events, such as errors, related to operation of the electronic device. The control system includes a controller for decreasing the operating voltage when the rate of timing events is below a target level and for increasing the operating voltage when the rate of timing events exceeds the target level to search for a threshold voltage that is the smallest operating voltage at which the rate of timing events is substantially at the target level. The control system further includes a controllable clock signal generator for producing a clock signal for operating the electronic device so that the clock frequency is according to an increasing function of the operating voltage. Thus, it is possible to find a voltage-frequency operating point where the energy consumption is minimized.

System and a method for controlling operating voltage

There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.

Control mechanism based on timing information

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

Growing community of inventors

Helsinki, Finland

Markus Hiienkari