International Business Machines Corporation

Markus Helms

Christian Jacobi

Frank Siegfried Lehnert

Uwe Brandt

Thomas G Koehler

Martin Recktenwald

Lisa Cranton Heller

Ute Gaertner

Jennifer A Navarro

Aditya Nitin Puranik

Markus Kaltenbach

Johannes C Reichart

Thomas Köhler

Jonathan D Bradbury

Anthony Saporito

Aaron Tsai

Ulrich Mayer

Christian Zoellin

Thomas Schlipf

Rebecca S Wisniewski

Parminder Singh

Christoph Raisch

Khary J Alexander

Bernd Nerz

Rolf Fritz

Gerd Konrad Bayer

Klaus Theurich

Volker Urban

Juergen Erwin Maergner

Wolfgang Eckert

Martin Eckert

Daniel D Sentler

Kirk David Lamb

Rainer Dorsch

Manfred Walz

Walter Heinrich Lipponer

Thomas Buechner

Harmut Ulland

Jürgen Märgner

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Translation support for a virtual cache

A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

Memory preserving parse tree based compression with entropy coding

A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Suspending translation look-aside buffer purge execution in a multi-processor environment

An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

Multi-engine address translation facility

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Zone-SDID mapping scheme for TLB purges

Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Optimizing data conversion using pattern frequency

Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

Sharing virtual and real translations in a virtual cache

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Boeblingen, Germany

Markus Helms