Advanced Micro Devices Corporation

Globalfoundries Inc.

Markus Forsberg

Roman Boschke

Manfred Horstmann

Andy C Wei

Sven Beyer

Peter Javorka

Maciej Wiatr

Frank Wirbeleit

Christoph Schwan

Karla Romero

Joe Bloomquist

Stephan Kronholz

Rolf Stephan

Martin Trentzsch

Anthony Mowry

Martin Gerhardt

Gert Burbach

By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

Semiconductor device having a high-K gate dielectric above an STI region

Method for self-aligned removal of a high-K gate dielectric above an STI region

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials

Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Semiconductor device comprising isolation trenches inducing different types of strain

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography

By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques.

SOI device having a substrate diode formed by reduced implantation energy

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

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Dresden, Germany

Markus Forsberg