Koninklijke Philips Corporation N.v.

Nxp B.v.

Markus Feuser

Peter Thueringer

Klaus Ully

Sabine Sommer

Adrianus Marinus Gerardus Peeters

Detlef Mueller

Peter Kompan

Torsten Kramer

Kurt Koenig

Detlef Müller

In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

Method and configuration for the transmission of signals from generating functional units to processing functional units of electrical circuits

An electronic memory component provides a plurality of access-secured sub-areas. Each access-secured memory sub-area has at least one assigned parameter, for example, an address. The memory encrypts the assigned parameters of the access-secured sub-areas in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great. The encryption allows access to at least one sub-area dependent on at least one further sub-area.

Address encryption method for flash memories

The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed. DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available. The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply. As a result the processes in the self-timed logic take place in an unpredictable way and current consumption becomes affected by severe noise and DPA cannot be successfully applied.

Method and arrangement for increasing the security of circuits against unauthorized access

The invention relates to a method and multiplier for multiplying two factors from the Galois field GF (2), where each of the factors can be represented as a vector of p sub-blocks with a width of m bits and p, m are positive integers greater than 1. The method and multiplier allow for a polynomial multiplication to be performed quickly and efficiently with minimum requirements in respect of for storage space. Therefore, savings can thus be achieved in respect of power consumption, crystal surface and calculation time.

Method for multiplying two factors from the Galois field and multiplier for performing the method

A digital microelectronic circuit comprises a clocked data-processing unit () and a converting unit () which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

Digital microelectronic circuit with a clocked data-processing unit and a converting unit

A data carrier that communicates confidential data is configured to mask process-dependent power consumption by using power stored in an internal capacitor. The capacitor is initially charged to the voltage of an external power source, and then decoupled from the external power source. The capacitor provides power to an internal processor, and consequently discharges gradually. At the end of a given time interval, the capacitor is discharged to a fixed voltage, then charged to the supply voltage. In this manner the power consumed by charging of the capacitor is decoupled from the power consumed by the processor. If the capacitor drops below a threshold voltage before processing is completed, the processor is halted. To optimize the available processing time, the time interval before discharging the capacitor to the fixed voltage is dynamically adjusted to reduce the time that the processor is halted.

Data carrier for the adaptation of a consumption time interval to the power consumption of the data carrier

An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

Arrangement with a microprocessor

A data carrier ( ) for the contactless communication of communication information (KD) with a transmitting/receiving station ( ) includes receiving circuit ( ) for receiving an HF signal (HF) containing the communication information (KD) from the transmitting/receiving station ( ), and processing circuit ( ) for processing the received communication information (KD), and supply voltage generating circuit ( ) for rectifying the received HF signal (HF) and for energizing the processing circuit ( ) with a supply voltage (UV), and reset circuit ( ) for resetting, when the supply voltage (UV) decreases below a reset voltage value (UR), the processing performed by the processing circuit ( ), the reset circuit ( ) now being adapted to interrupt the processing of the communication information (KD) by the processing circuit ( ) at least partially when the supply voltage (UV) decreases below an interruption voltage value (UU), the interruption voltage value (UU) being greater than the reset voltage value (UR).

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Hamburg, Germany

Markus Feuser